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539 lines
18 KiB
539 lines
18 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __HEAD_BOOKE_H__ |
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#define __HEAD_BOOKE_H__ |
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#include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */ |
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#include <asm/kvm_asm.h> |
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#include <asm/kvm_booke_hv_asm.h> |
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#ifdef __ASSEMBLY__ |
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/* |
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* Macros used for common Book-e exception handling |
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*/ |
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#define SET_IVOR(vector_number, vector_label) \ |
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li r26,vector_label@l; \ |
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mtspr SPRN_IVOR##vector_number,r26; \ |
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sync |
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#if (THREAD_SHIFT < 15) |
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#define ALLOC_STACK_FRAME(reg, val) \ |
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addi reg,reg,val |
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#else |
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#define ALLOC_STACK_FRAME(reg, val) \ |
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addis reg,reg,val@ha; \ |
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addi reg,reg,val@l |
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#endif |
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/* |
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* Macro used to get to thread save registers. |
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* Note that entries 0-3 are used for the prolog code, and the remaining |
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* entries are available for specific exception use in the event a handler |
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* requires more than 4 scratch registers. |
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*/ |
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#define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4)) |
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#ifdef CONFIG_PPC_FSL_BOOK3E |
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#define BOOKE_CLEAR_BTB(reg) \ |
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START_BTB_FLUSH_SECTION \ |
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BTB_FLUSH(reg) \ |
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END_BTB_FLUSH_SECTION |
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#else |
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#define BOOKE_CLEAR_BTB(reg) |
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#endif |
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#define NORMAL_EXCEPTION_PROLOG(trapno, intno) \ |
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mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ |
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mfspr r10, SPRN_SPRG_THREAD; \ |
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stw r11, THREAD_NORMSAVE(0)(r10); \ |
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stw r13, THREAD_NORMSAVE(2)(r10); \ |
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mfcr r13; /* save CR in r13 for now */\ |
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mfspr r11, SPRN_SRR1; \ |
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DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \ |
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andi. r11, r11, MSR_PR; /* check whether user or kernel */\ |
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LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \ |
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mtmsr r11; \ |
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mr r11, r1; \ |
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beq 1f; \ |
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BOOKE_CLEAR_BTB(r11) \ |
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/* if from user, start at top of this thread's kernel stack */ \ |
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lwz r11, TASK_STACK - THREAD(r10); \ |
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ALLOC_STACK_FRAME(r11, THREAD_SIZE); \ |
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1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \ |
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stw r13, _CCR(r11); /* save various registers */ \ |
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stw r12,GPR12(r11); \ |
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stw r9,GPR9(r11); \ |
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mfspr r13, SPRN_SPRG_RSCRATCH0; \ |
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stw r13, GPR10(r11); \ |
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lwz r12, THREAD_NORMSAVE(0)(r10); \ |
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stw r12,GPR11(r11); \ |
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lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \ |
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mflr r10; \ |
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stw r10,_LINK(r11); \ |
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mfspr r12,SPRN_SRR0; \ |
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stw r1, GPR1(r11); \ |
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mfspr r9,SPRN_SRR1; \ |
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stw r1, 0(r11); \ |
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mr r1, r11; \ |
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rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ |
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COMMON_EXCEPTION_PROLOG_END trapno |
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.macro COMMON_EXCEPTION_PROLOG_END trapno |
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stw r0,GPR0(r1) |
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lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ |
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addi r10, r10, STACK_FRAME_REGS_MARKER@l |
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stw r10, 8(r1) |
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li r10, \trapno |
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stw r10,_TRAP(r1) |
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SAVE_4GPRS(3, r1) |
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SAVE_2GPRS(7, r1) |
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SAVE_NVGPRS(r1) |
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stw r2,GPR2(r1) |
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stw r12,_NIP(r1) |
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stw r9,_MSR(r1) |
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mfctr r10 |
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mfspr r2,SPRN_SPRG_THREAD |
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stw r10,_CTR(r1) |
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tovirt(r2, r2) |
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mfspr r10,SPRN_XER |
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addi r2, r2, -THREAD |
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stw r10,_XER(r1) |
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addi r3,r1,STACK_FRAME_OVERHEAD |
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.endm |
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.macro prepare_transfer_to_handler |
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#ifdef CONFIG_E500 |
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andi. r12,r9,MSR_PR |
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bne 777f |
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bl prepare_transfer_to_handler |
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777: |
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#endif |
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.endm |
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.macro SYSCALL_ENTRY trapno intno srr1 |
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mfspr r10, SPRN_SPRG_THREAD |
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#ifdef CONFIG_KVM_BOOKE_HV |
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BEGIN_FTR_SECTION |
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mtspr SPRN_SPRG_WSCRATCH0, r10 |
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stw r11, THREAD_NORMSAVE(0)(r10) |
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stw r13, THREAD_NORMSAVE(2)(r10) |
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mfcr r13 /* save CR in r13 for now */ |
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mfspr r11, SPRN_SRR1 |
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mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */ |
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bf 3, 1975f |
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b kvmppc_handler_\intno\()_\srr1 |
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1975: |
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mr r12, r13 |
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lwz r13, THREAD_NORMSAVE(2)(r10) |
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FTR_SECTION_ELSE |
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mfcr r12 |
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ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV) |
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#else |
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mfcr r12 |
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#endif |
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mfspr r9, SPRN_SRR1 |
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BOOKE_CLEAR_BTB(r11) |
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mr r11, r1 |
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lwz r1, TASK_STACK - THREAD(r10) |
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rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */ |
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ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE) |
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stw r12, _CCR(r1) |
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mfspr r12,SPRN_SRR0 |
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stw r12,_NIP(r1) |
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b transfer_to_syscall /* jump to handler */ |
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.endm |
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/* To handle the additional exception priority levels on 40x and Book-E |
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* processors we allocate a stack per additional priority level. |
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* |
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* On 40x critical is the only additional level |
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* On 44x/e500 we have critical and machine check |
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* |
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* Additionally we reserve a SPRG for each priority level so we can free up a |
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* GPR to use as the base for indirect access to the exception stacks. This |
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* is necessary since the MMU is always on, for Book-E parts, and the stacks |
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* are offset from KERNELBASE. |
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* |
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* There is some space optimization to be had here if desired. However |
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* to allow for a common kernel with support for debug exceptions either |
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* going to critical or their own debug level we aren't currently |
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* providing configurations that micro-optimize space usage. |
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*/ |
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#define MC_STACK_BASE mcheckirq_ctx |
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#define CRIT_STACK_BASE critirq_ctx |
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/* only on e500mc */ |
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#define DBG_STACK_BASE dbgirq_ctx |
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#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE) |
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#ifdef CONFIG_SMP |
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#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ |
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mfspr r8,SPRN_PIR; \ |
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slwi r8,r8,2; \ |
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addis r8,r8,level##_STACK_BASE@ha; \ |
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lwz r8,level##_STACK_BASE@l(r8); \ |
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addi r8,r8,EXC_LVL_FRAME_OVERHEAD; |
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#else |
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#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ |
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lis r8,level##_STACK_BASE@ha; \ |
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lwz r8,level##_STACK_BASE@l(r8); \ |
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addi r8,r8,EXC_LVL_FRAME_OVERHEAD; |
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#endif |
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/* |
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* Exception prolog for critical/machine check exceptions. This is a |
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* little different from the normal exception prolog above since a |
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* critical/machine check exception can potentially occur at any point |
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* during normal exception processing. Thus we cannot use the same SPRG |
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* registers as the normal prolog above. Instead we use a portion of the |
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* critical/machine check exception stack at low physical addresses. |
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*/ |
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#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \ |
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mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \ |
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BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \ |
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stw r9,GPR9(r8); /* save various registers */\ |
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mfcr r9; /* save CR in r9 for now */\ |
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stw r10,GPR10(r8); \ |
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stw r11,GPR11(r8); \ |
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stw r9,_CCR(r8); /* save CR on stack */\ |
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mfspr r11,exc_level_srr1; /* check whether user or kernel */\ |
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DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \ |
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BOOKE_CLEAR_BTB(r10) \ |
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andi. r11,r11,MSR_PR; \ |
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LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ |
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mtmsr r11; \ |
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mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\ |
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lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\ |
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addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\ |
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beq 1f; \ |
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/* COMING FROM USER MODE */ \ |
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stw r9,_CCR(r11); /* save CR */\ |
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lwz r10,GPR10(r8); /* copy regs from exception stack */\ |
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lwz r9,GPR9(r8); \ |
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stw r10,GPR10(r11); \ |
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lwz r10,GPR11(r8); \ |
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stw r9,GPR9(r11); \ |
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stw r10,GPR11(r11); \ |
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b 2f; \ |
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/* COMING FROM PRIV MODE */ \ |
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1: mr r11, r8; \ |
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2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \ |
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stw r12,GPR12(r11); /* save various registers */\ |
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mflr r10; \ |
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stw r10,_LINK(r11); \ |
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mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\ |
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stw r12,_DEAR(r11); /* since they may have had stuff */\ |
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mfspr r9,SPRN_ESR; /* in them at the point where the */\ |
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stw r9,_ESR(r11); /* exception was taken */\ |
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mfspr r12,exc_level_srr0; \ |
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stw r1,GPR1(r11); \ |
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mfspr r9,exc_level_srr1; \ |
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stw r1,0(r11); \ |
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mr r1,r11; \ |
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rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\ |
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COMMON_EXCEPTION_PROLOG_END trapno |
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#define SAVE_xSRR(xSRR) \ |
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mfspr r0,SPRN_##xSRR##0; \ |
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stw r0,_##xSRR##0(r1); \ |
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mfspr r0,SPRN_##xSRR##1; \ |
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stw r0,_##xSRR##1(r1) |
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.macro SAVE_MMU_REGS |
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#ifdef CONFIG_PPC_BOOK3E_MMU |
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mfspr r0,SPRN_MAS0 |
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stw r0,MAS0(r1) |
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mfspr r0,SPRN_MAS1 |
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stw r0,MAS1(r1) |
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mfspr r0,SPRN_MAS2 |
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stw r0,MAS2(r1) |
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mfspr r0,SPRN_MAS3 |
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stw r0,MAS3(r1) |
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mfspr r0,SPRN_MAS6 |
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stw r0,MAS6(r1) |
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#ifdef CONFIG_PHYS_64BIT |
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mfspr r0,SPRN_MAS7 |
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stw r0,MAS7(r1) |
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#endif /* CONFIG_PHYS_64BIT */ |
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#endif /* CONFIG_PPC_BOOK3E_MMU */ |
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#ifdef CONFIG_44x |
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mfspr r0,SPRN_MMUCR |
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stw r0,MMUCR(r1) |
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#endif |
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.endm |
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#define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \ |
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EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1) |
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#define DEBUG_EXCEPTION_PROLOG(trapno) \ |
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EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1) |
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#define MCHECK_EXCEPTION_PROLOG(trapno) \ |
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EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \ |
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SPRN_MCSRR0, SPRN_MCSRR1) |
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/* |
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* Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite |
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* being delivered to the host. This exception can only happen |
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* inside a KVM guest -- so we just handle up to the DO_KVM rather |
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* than try to fit this into one of the existing prolog macros. |
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*/ |
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#define GUEST_DOORBELL_EXCEPTION \ |
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START_EXCEPTION(GuestDoorbell); \ |
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mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \ |
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mfspr r10, SPRN_SPRG_THREAD; \ |
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stw r11, THREAD_NORMSAVE(0)(r10); \ |
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mfspr r11, SPRN_SRR1; \ |
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stw r13, THREAD_NORMSAVE(2)(r10); \ |
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mfcr r13; /* save CR in r13 for now */\ |
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DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \ |
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trap |
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/* |
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* Exception vectors. |
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*/ |
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#define START_EXCEPTION(label) \ |
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.align 5; \ |
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label: |
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#define EXCEPTION(n, intno, label, hdlr) \ |
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START_EXCEPTION(label); \ |
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NORMAL_EXCEPTION_PROLOG(n, intno); \ |
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prepare_transfer_to_handler; \ |
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bl hdlr; \ |
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b interrupt_return |
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#define CRITICAL_EXCEPTION(n, intno, label, hdlr) \ |
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START_EXCEPTION(label); \ |
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CRITICAL_EXCEPTION_PROLOG(n, intno); \ |
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SAVE_MMU_REGS; \ |
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SAVE_xSRR(SRR); \ |
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prepare_transfer_to_handler; \ |
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bl hdlr; \ |
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b ret_from_crit_exc |
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#define MCHECK_EXCEPTION(n, label, hdlr) \ |
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START_EXCEPTION(label); \ |
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MCHECK_EXCEPTION_PROLOG(n); \ |
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mfspr r5,SPRN_ESR; \ |
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stw r5,_ESR(r11); \ |
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SAVE_xSRR(DSRR); \ |
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SAVE_xSRR(CSRR); \ |
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SAVE_MMU_REGS; \ |
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SAVE_xSRR(SRR); \ |
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prepare_transfer_to_handler; \ |
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bl hdlr; \ |
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b ret_from_mcheck_exc |
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/* Check for a single step debug exception while in an exception |
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* handler before state has been saved. This is to catch the case |
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* where an instruction that we are trying to single step causes |
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* an exception (eg ITLB/DTLB miss) and thus the first instruction of |
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* the exception handler generates a single step debug exception. |
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* |
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* If we get a debug trap on the first instruction of an exception handler, |
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* we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is |
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* a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR). |
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* The exception handler was handling a non-critical interrupt, so it will |
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* save (and later restore) the MSR via SPRN_CSRR1, which will still have |
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* the MSR_DE bit set. |
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*/ |
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#define DEBUG_DEBUG_EXCEPTION \ |
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START_EXCEPTION(DebugDebug); \ |
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DEBUG_EXCEPTION_PROLOG(2000); \ |
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\ |
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/* \ |
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* If there is a single step or branch-taken exception in an \ |
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* exception entry sequence, it was probably meant to apply to \ |
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* the code where the exception occurred (since exception entry \ |
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* doesn't turn off DE automatically). We simulate the effect \ |
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* of turning off DE on entry to an exception handler by turning \ |
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* off DE in the DSRR1 value and clearing the debug status. \ |
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*/ \ |
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mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ |
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andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ |
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beq+ 2f; \ |
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\ |
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lis r10,interrupt_base@h; /* check if exception in vectors */ \ |
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ori r10,r10,interrupt_base@l; \ |
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cmplw r12,r10; \ |
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blt+ 2f; /* addr below exception vectors */ \ |
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\ |
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lis r10,interrupt_end@h; \ |
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ori r10,r10,interrupt_end@l; \ |
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cmplw r12,r10; \ |
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bgt+ 2f; /* addr above exception vectors */ \ |
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\ |
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/* here it looks like we got an inappropriate debug exception. */ \ |
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1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ |
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lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ |
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mtspr SPRN_DBSR,r10; \ |
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/* restore state and get out */ \ |
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lwz r10,_CCR(r11); \ |
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lwz r0,GPR0(r11); \ |
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lwz r1,GPR1(r11); \ |
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mtcrf 0x80,r10; \ |
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mtspr SPRN_DSRR0,r12; \ |
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mtspr SPRN_DSRR1,r9; \ |
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lwz r9,GPR9(r11); \ |
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lwz r12,GPR12(r11); \ |
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mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \ |
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BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \ |
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lwz r10,GPR10(r8); \ |
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lwz r11,GPR11(r8); \ |
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mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \ |
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\ |
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PPC_RFDI; \ |
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b .; \ |
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\ |
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/* continue normal handling for a debug exception... */ \ |
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2: mfspr r4,SPRN_DBSR; \ |
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stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\ |
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SAVE_xSRR(CSRR); \ |
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SAVE_MMU_REGS; \ |
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SAVE_xSRR(SRR); \ |
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prepare_transfer_to_handler; \ |
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bl DebugException; \ |
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b ret_from_debug_exc |
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#define DEBUG_CRIT_EXCEPTION \ |
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START_EXCEPTION(DebugCrit); \ |
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CRITICAL_EXCEPTION_PROLOG(2000,DEBUG); \ |
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\ |
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/* \ |
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* If there is a single step or branch-taken exception in an \ |
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* exception entry sequence, it was probably meant to apply to \ |
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* the code where the exception occurred (since exception entry \ |
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* doesn't turn off DE automatically). We simulate the effect \ |
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* of turning off DE on entry to an exception handler by turning \ |
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* off DE in the CSRR1 value and clearing the debug status. \ |
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*/ \ |
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mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ |
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andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \ |
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beq+ 2f; \ |
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\ |
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lis r10,interrupt_base@h; /* check if exception in vectors */ \ |
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ori r10,r10,interrupt_base@l; \ |
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cmplw r12,r10; \ |
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blt+ 2f; /* addr below exception vectors */ \ |
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\ |
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lis r10,interrupt_end@h; \ |
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ori r10,r10,interrupt_end@l; \ |
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cmplw r12,r10; \ |
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bgt+ 2f; /* addr above exception vectors */ \ |
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\ |
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/* here it looks like we got an inappropriate debug exception. */ \ |
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1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ |
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lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \ |
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mtspr SPRN_DBSR,r10; \ |
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/* restore state and get out */ \ |
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lwz r10,_CCR(r11); \ |
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lwz r0,GPR0(r11); \ |
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lwz r1,GPR1(r11); \ |
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mtcrf 0x80,r10; \ |
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mtspr SPRN_CSRR0,r12; \ |
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mtspr SPRN_CSRR1,r9; \ |
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lwz r9,GPR9(r11); \ |
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lwz r12,GPR12(r11); \ |
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mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \ |
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BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \ |
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lwz r10,GPR10(r8); \ |
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lwz r11,GPR11(r8); \ |
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mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \ |
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\ |
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rfci; \ |
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b .; \ |
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\ |
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/* continue normal handling for a critical exception... */ \ |
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2: mfspr r4,SPRN_DBSR; \ |
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stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\ |
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SAVE_MMU_REGS; \ |
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SAVE_xSRR(SRR); \ |
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prepare_transfer_to_handler; \ |
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bl DebugException; \ |
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b ret_from_crit_exc |
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|
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#define DATA_STORAGE_EXCEPTION \ |
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START_EXCEPTION(DataStorage) \ |
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NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE); \ |
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mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ |
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stw r5,_ESR(r11); \ |
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mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \ |
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stw r4, _DEAR(r11); \ |
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prepare_transfer_to_handler; \ |
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bl do_page_fault; \ |
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b interrupt_return |
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|
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#define INSTRUCTION_STORAGE_EXCEPTION \ |
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START_EXCEPTION(InstructionStorage) \ |
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NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \ |
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mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \ |
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stw r5,_ESR(r11); \ |
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stw r12, _DEAR(r11); /* Pass SRR0 as arg2 */ \ |
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prepare_transfer_to_handler; \ |
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bl do_page_fault; \ |
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b interrupt_return |
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|
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#define ALIGNMENT_EXCEPTION \ |
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START_EXCEPTION(Alignment) \ |
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NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT); \ |
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mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \ |
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stw r4,_DEAR(r11); \ |
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prepare_transfer_to_handler; \ |
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bl alignment_exception; \ |
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REST_NVGPRS(r1); \ |
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b interrupt_return |
|
|
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#define PROGRAM_EXCEPTION \ |
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START_EXCEPTION(Program) \ |
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NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM); \ |
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mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \ |
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stw r4,_ESR(r11); \ |
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prepare_transfer_to_handler; \ |
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bl program_check_exception; \ |
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REST_NVGPRS(r1); \ |
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b interrupt_return |
|
|
|
#define DECREMENTER_EXCEPTION \ |
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START_EXCEPTION(Decrementer) \ |
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NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER); \ |
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lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \ |
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mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \ |
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prepare_transfer_to_handler; \ |
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bl timer_interrupt; \ |
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b interrupt_return |
|
|
|
#define FP_UNAVAILABLE_EXCEPTION \ |
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START_EXCEPTION(FloatingPointUnavailable) \ |
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NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL); \ |
|
beq 1f; \ |
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bl load_up_fpu; /* if from user, just load it up */ \ |
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b fast_exception_return; \ |
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1: prepare_transfer_to_handler; \ |
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bl kernel_fp_unavailable_exception; \ |
|
b interrupt_return |
|
|
|
#else /* __ASSEMBLY__ */ |
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struct exception_regs { |
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unsigned long mas0; |
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unsigned long mas1; |
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unsigned long mas2; |
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unsigned long mas3; |
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unsigned long mas6; |
|
unsigned long mas7; |
|
unsigned long srr0; |
|
unsigned long srr1; |
|
unsigned long csrr0; |
|
unsigned long csrr1; |
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unsigned long dsrr0; |
|
unsigned long dsrr1; |
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}; |
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|
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/* ensure this structure is always sized to a multiple of the stack alignment */ |
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#define STACK_EXC_LVL_FRAME_SIZE ALIGN(sizeof (struct exception_regs), 16) |
|
|
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#endif /* __ASSEMBLY__ */ |
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#endif /* __HEAD_BOOKE_H__ */
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