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582 lines
14 KiB
582 lines
14 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* PowerPC version |
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
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* Rewritten by Cort Dougan (cort@fsmlabs.com) for PReP |
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* Copyright (C) 1996 Cort Dougan <cort@fsmlabs.com> |
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* Adapted for Power Macintosh by Paul Mackerras. |
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* Low-level exception handlers and MMU support |
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* rewritten by Paul Mackerras. |
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* Copyright (C) 1996 Paul Mackerras. |
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* MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net). |
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* |
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* This file contains the system call entry code, context switch |
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* code, and exception/interrupt return code for PowerPC. |
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*/ |
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|
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#include <linux/errno.h> |
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#include <linux/err.h> |
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#include <linux/sys.h> |
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#include <linux/threads.h> |
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#include <asm/reg.h> |
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#include <asm/page.h> |
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#include <asm/mmu.h> |
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#include <asm/cputable.h> |
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#include <asm/thread_info.h> |
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#include <asm/ppc_asm.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/unistd.h> |
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#include <asm/ptrace.h> |
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#include <asm/export.h> |
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#include <asm/feature-fixups.h> |
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#include <asm/barrier.h> |
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#include <asm/kup.h> |
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#include <asm/bug.h> |
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#include <asm/interrupt.h> |
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|
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#include "head_32.h" |
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|
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/* |
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* powerpc relies on return from interrupt/syscall being context synchronising |
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* (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional |
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* synchronisation instructions. |
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*/ |
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|
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/* |
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* Align to 4k in order to ensure that all functions modyfing srr0/srr1 |
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* fit into one page in order to not encounter a TLB miss between the |
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* modification of srr0/srr1 and the associated rfi. |
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*/ |
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.align 12 |
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#if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_E500) |
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.globl prepare_transfer_to_handler |
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prepare_transfer_to_handler: |
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/* if from kernel, check interrupted DOZE/NAP mode */ |
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lwz r12,TI_LOCAL_FLAGS(r2) |
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mtcrf 0x01,r12 |
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bt- 31-TLF_NAPPING,4f |
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bt- 31-TLF_SLEEPING,7f |
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blr |
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4: rlwinm r12,r12,0,~_TLF_NAPPING |
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stw r12,TI_LOCAL_FLAGS(r2) |
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b power_save_ppc32_restore |
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|
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7: rlwinm r12,r12,0,~_TLF_SLEEPING |
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stw r12,TI_LOCAL_FLAGS(r2) |
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lwz r9,_MSR(r11) /* if sleeping, clear MSR.EE */ |
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rlwinm r9,r9,0,~MSR_EE |
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lwz r12,_LINK(r11) /* and return to address in LR */ |
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lwz r2, GPR2(r11) |
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b fast_exception_return |
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_ASM_NOKPROBE_SYMBOL(prepare_transfer_to_handler) |
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#endif /* CONFIG_PPC_BOOK3S_32 || CONFIG_E500 */ |
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.globl transfer_to_syscall |
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transfer_to_syscall: |
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stw r11, GPR1(r1) |
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stw r11, 0(r1) |
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mflr r12 |
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stw r12, _LINK(r1) |
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#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) |
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rlwinm r9,r9,0,14,12 /* clear MSR_WE (necessary?) */ |
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#endif |
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lis r12,STACK_FRAME_REGS_MARKER@ha /* exception frame marker */ |
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SAVE_GPR(2, r1) |
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addi r12,r12,STACK_FRAME_REGS_MARKER@l |
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stw r9,_MSR(r1) |
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li r2, INTERRUPT_SYSCALL |
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stw r12,8(r1) |
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stw r2,_TRAP(r1) |
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SAVE_GPR(0, r1) |
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SAVE_4GPRS(3, r1) |
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SAVE_2GPRS(7, r1) |
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addi r2,r10,-THREAD |
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SAVE_NVGPRS(r1) |
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|
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/* Calling convention has r9 = orig r0, r10 = regs */ |
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addi r10,r1,STACK_FRAME_OVERHEAD |
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mr r9,r0 |
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bl system_call_exception |
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ret_from_syscall: |
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addi r4,r1,STACK_FRAME_OVERHEAD |
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li r5,0 |
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bl syscall_exit_prepare |
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#ifdef CONFIG_PPC_47x |
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lis r4,icache_44x_need_flush@ha |
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lwz r5,icache_44x_need_flush@l(r4) |
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cmplwi cr0,r5,0 |
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bne- 2f |
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#endif /* CONFIG_PPC_47x */ |
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lwz r4,_LINK(r1) |
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lwz r5,_CCR(r1) |
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mtlr r4 |
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lwz r7,_NIP(r1) |
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lwz r8,_MSR(r1) |
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cmpwi r3,0 |
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lwz r3,GPR3(r1) |
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syscall_exit_finish: |
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mtspr SPRN_SRR0,r7 |
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mtspr SPRN_SRR1,r8 |
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bne 3f |
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mtcr r5 |
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1: lwz r2,GPR2(r1) |
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lwz r1,GPR1(r1) |
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rfi |
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#ifdef CONFIG_40x |
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b . /* Prevent prefetch past rfi */ |
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#endif |
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|
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3: mtcr r5 |
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lwz r4,_CTR(r1) |
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lwz r5,_XER(r1) |
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REST_NVGPRS(r1) |
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mtctr r4 |
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mtxer r5 |
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lwz r0,GPR0(r1) |
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lwz r3,GPR3(r1) |
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REST_8GPRS(4,r1) |
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lwz r12,GPR12(r1) |
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b 1b |
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#ifdef CONFIG_44x |
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2: li r7,0 |
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iccci r0,r0 |
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stw r7,icache_44x_need_flush@l(r4) |
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b 1b |
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#endif /* CONFIG_44x */ |
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.globl ret_from_fork |
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ret_from_fork: |
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REST_NVGPRS(r1) |
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bl schedule_tail |
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li r3,0 |
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b ret_from_syscall |
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.globl ret_from_kernel_thread |
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ret_from_kernel_thread: |
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REST_NVGPRS(r1) |
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bl schedule_tail |
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mtlr r14 |
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mr r3,r15 |
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PPC440EP_ERR42 |
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blrl |
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li r3,0 |
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b ret_from_syscall |
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/* |
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* This routine switches between two different tasks. The process |
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* state of one is saved on its kernel stack. Then the state |
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* of the other is restored from its kernel stack. The memory |
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* management hardware is updated to the second process's state. |
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* Finally, we can return to the second process. |
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* On entry, r3 points to the THREAD for the current task, r4 |
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* points to the THREAD for the new task. |
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* |
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* This routine is always called with interrupts disabled. |
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* |
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* Note: there are two ways to get to the "going out" portion |
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* of this code; either by coming in via the entry (_switch) |
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* or via "fork" which must set up an environment equivalent |
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* to the "_switch" path. If you change this , you'll have to |
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* change the fork code also. |
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* |
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* The code which creates the new task context is in 'copy_thread' |
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* in arch/ppc/kernel/process.c |
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*/ |
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_GLOBAL(_switch) |
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stwu r1,-INT_FRAME_SIZE(r1) |
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mflr r0 |
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stw r0,INT_FRAME_SIZE+4(r1) |
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/* r3-r12 are caller saved -- Cort */ |
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SAVE_NVGPRS(r1) |
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stw r0,_NIP(r1) /* Return to switch caller */ |
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mfcr r10 |
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stw r10,_CCR(r1) |
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stw r1,KSP(r3) /* Set old stack pointer */ |
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#ifdef CONFIG_SMP |
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/* We need a sync somewhere here to make sure that if the |
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* previous task gets rescheduled on another CPU, it sees all |
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* stores it has performed on this one. |
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*/ |
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sync |
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#endif /* CONFIG_SMP */ |
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tophys(r0,r4) |
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mtspr SPRN_SPRG_THREAD,r0 /* Update current THREAD phys addr */ |
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lwz r1,KSP(r4) /* Load new stack pointer */ |
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|
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/* save the old current 'last' for return value */ |
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mr r3,r2 |
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addi r2,r4,-THREAD /* Update current */ |
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lwz r0,_CCR(r1) |
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mtcrf 0xFF,r0 |
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/* r3-r12 are destroyed -- Cort */ |
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REST_NVGPRS(r1) |
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|
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lwz r4,_NIP(r1) /* Return to _switch caller in new task */ |
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mtlr r4 |
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addi r1,r1,INT_FRAME_SIZE |
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blr |
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.globl fast_exception_return |
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fast_exception_return: |
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#if !(defined(CONFIG_4xx) || defined(CONFIG_BOOKE)) |
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andi. r10,r9,MSR_RI /* check for recoverable interrupt */ |
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beq 3f /* if not, we've got problems */ |
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#endif |
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2: REST_4GPRS(3, r11) |
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lwz r10,_CCR(r11) |
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REST_2GPRS(1, r11) |
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mtcr r10 |
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lwz r10,_LINK(r11) |
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mtlr r10 |
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/* Clear the exception_marker on the stack to avoid confusing stacktrace */ |
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li r10, 0 |
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stw r10, 8(r11) |
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REST_GPR(10, r11) |
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#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PERF_EVENTS) |
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mtspr SPRN_NRI, r0 |
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#endif |
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mtspr SPRN_SRR1,r9 |
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mtspr SPRN_SRR0,r12 |
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REST_GPR(9, r11) |
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REST_GPR(12, r11) |
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lwz r11,GPR11(r11) |
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rfi |
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#ifdef CONFIG_40x |
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b . /* Prevent prefetch past rfi */ |
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#endif |
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_ASM_NOKPROBE_SYMBOL(fast_exception_return) |
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|
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/* aargh, a nonrecoverable interrupt, panic */ |
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/* aargh, we don't know which trap this is */ |
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3: |
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li r10,-1 |
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stw r10,_TRAP(r11) |
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prepare_transfer_to_handler |
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bl unrecoverable_exception |
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trap /* should not get here */ |
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.globl interrupt_return |
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interrupt_return: |
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lwz r4,_MSR(r1) |
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addi r3,r1,STACK_FRAME_OVERHEAD |
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andi. r0,r4,MSR_PR |
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beq .Lkernel_interrupt_return |
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bl interrupt_exit_user_prepare |
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cmpwi r3,0 |
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bne- .Lrestore_nvgprs |
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.Lfast_user_interrupt_return: |
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lwz r11,_NIP(r1) |
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lwz r12,_MSR(r1) |
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mtspr SPRN_SRR0,r11 |
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mtspr SPRN_SRR1,r12 |
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BEGIN_FTR_SECTION |
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stwcx. r0,0,r1 /* to clear the reservation */ |
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FTR_SECTION_ELSE |
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lwarx r0,0,r1 |
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
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|
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lwz r3,_CCR(r1) |
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lwz r4,_LINK(r1) |
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lwz r5,_CTR(r1) |
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lwz r6,_XER(r1) |
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li r0,0 |
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/* |
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* Leaving a stale exception_marker on the stack can confuse |
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* the reliable stack unwinder later on. Clear it. |
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*/ |
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stw r0,8(r1) |
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REST_4GPRS(7, r1) |
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REST_2GPRS(11, r1) |
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mtcr r3 |
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mtlr r4 |
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mtctr r5 |
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mtspr SPRN_XER,r6 |
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REST_4GPRS(2, r1) |
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REST_GPR(6, r1) |
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REST_GPR(0, r1) |
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REST_GPR(1, r1) |
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rfi |
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#ifdef CONFIG_40x |
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b . /* Prevent prefetch past rfi */ |
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#endif |
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.Lrestore_nvgprs: |
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REST_NVGPRS(r1) |
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b .Lfast_user_interrupt_return |
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.Lkernel_interrupt_return: |
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bl interrupt_exit_kernel_prepare |
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.Lfast_kernel_interrupt_return: |
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cmpwi cr1,r3,0 |
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lwz r11,_NIP(r1) |
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lwz r12,_MSR(r1) |
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mtspr SPRN_SRR0,r11 |
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mtspr SPRN_SRR1,r12 |
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BEGIN_FTR_SECTION |
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stwcx. r0,0,r1 /* to clear the reservation */ |
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FTR_SECTION_ELSE |
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lwarx r0,0,r1 |
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ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS) |
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|
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lwz r3,_LINK(r1) |
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lwz r4,_CTR(r1) |
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lwz r5,_XER(r1) |
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lwz r6,_CCR(r1) |
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li r0,0 |
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REST_4GPRS(7, r1) |
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REST_2GPRS(11, r1) |
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mtlr r3 |
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mtctr r4 |
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mtspr SPRN_XER,r5 |
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|
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/* |
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* Leaving a stale exception_marker on the stack can confuse |
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* the reliable stack unwinder later on. Clear it. |
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*/ |
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stw r0,8(r1) |
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REST_4GPRS(2, r1) |
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|
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bne- cr1,1f /* emulate stack store */ |
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mtcr r6 |
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REST_GPR(6, r1) |
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REST_GPR(0, r1) |
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REST_GPR(1, r1) |
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rfi |
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#ifdef CONFIG_40x |
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b . /* Prevent prefetch past rfi */ |
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#endif |
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1: /* |
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* Emulate stack store with update. New r1 value was already calculated |
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* and updated in our interrupt regs by emulate_loadstore, but we can't |
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* store the previous value of r1 to the stack before re-loading our |
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* registers from it, otherwise they could be clobbered. Use |
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* SPRG Scratch0 as temporary storage to hold the store |
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* data, as interrupts are disabled here so it won't be clobbered. |
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*/ |
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mtcr r6 |
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#ifdef CONFIG_BOOKE |
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mtspr SPRN_SPRG_WSCRATCH0, r9 |
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#else |
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mtspr SPRN_SPRG_SCRATCH0, r9 |
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#endif |
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addi r9,r1,INT_FRAME_SIZE /* get original r1 */ |
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REST_GPR(6, r1) |
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REST_GPR(0, r1) |
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REST_GPR(1, r1) |
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stw r9,0(r1) /* perform store component of stwu */ |
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#ifdef CONFIG_BOOKE |
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mfspr r9, SPRN_SPRG_RSCRATCH0 |
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#else |
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mfspr r9, SPRN_SPRG_SCRATCH0 |
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#endif |
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rfi |
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#ifdef CONFIG_40x |
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b . /* Prevent prefetch past rfi */ |
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#endif |
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_ASM_NOKPROBE_SYMBOL(interrupt_return) |
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|
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#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) |
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|
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/* |
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* Returning from a critical interrupt in user mode doesn't need |
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* to be any different from a normal exception. For a critical |
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* interrupt in the kernel, we just return (without checking for |
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* preemption) since the interrupt may have happened at some crucial |
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* place (e.g. inside the TLB miss handler), and because we will be |
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* running with r1 pointing into critical_stack, not the current |
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* process's kernel stack (and therefore current_thread_info() will |
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* give the wrong answer). |
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* We have to restore various SPRs that may have been in use at the |
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* time of the critical interrupt. |
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* |
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*/ |
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#ifdef CONFIG_40x |
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#define PPC_40x_TURN_OFF_MSR_DR \ |
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/* avoid any possible TLB misses here by turning off MSR.DR, we \ |
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* assume the instructions here are mapped by a pinned TLB entry */ \ |
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li r10,MSR_IR; \ |
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mtmsr r10; \ |
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isync; \ |
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tophys(r1, r1); |
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#else |
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#define PPC_40x_TURN_OFF_MSR_DR |
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#endif |
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|
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#define RET_FROM_EXC_LEVEL(exc_lvl_srr0, exc_lvl_srr1, exc_lvl_rfi) \ |
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REST_NVGPRS(r1); \ |
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lwz r3,_MSR(r1); \ |
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andi. r3,r3,MSR_PR; \ |
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bne interrupt_return; \ |
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lwz r0,GPR0(r1); \ |
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lwz r2,GPR2(r1); \ |
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REST_4GPRS(3, r1); \ |
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REST_2GPRS(7, r1); \ |
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lwz r10,_XER(r1); \ |
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lwz r11,_CTR(r1); \ |
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mtspr SPRN_XER,r10; \ |
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mtctr r11; \ |
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stwcx. r0,0,r1; /* to clear the reservation */ \ |
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lwz r11,_LINK(r1); \ |
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mtlr r11; \ |
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lwz r10,_CCR(r1); \ |
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mtcrf 0xff,r10; \ |
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PPC_40x_TURN_OFF_MSR_DR; \ |
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lwz r9,_DEAR(r1); \ |
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lwz r10,_ESR(r1); \ |
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mtspr SPRN_DEAR,r9; \ |
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mtspr SPRN_ESR,r10; \ |
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lwz r11,_NIP(r1); \ |
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lwz r12,_MSR(r1); \ |
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mtspr exc_lvl_srr0,r11; \ |
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mtspr exc_lvl_srr1,r12; \ |
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lwz r9,GPR9(r1); \ |
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lwz r12,GPR12(r1); \ |
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lwz r10,GPR10(r1); \ |
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lwz r11,GPR11(r1); \ |
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lwz r1,GPR1(r1); \ |
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exc_lvl_rfi; \ |
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b .; /* prevent prefetch past exc_lvl_rfi */ |
|
|
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#define RESTORE_xSRR(exc_lvl_srr0, exc_lvl_srr1) \ |
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lwz r9,_##exc_lvl_srr0(r1); \ |
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lwz r10,_##exc_lvl_srr1(r1); \ |
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mtspr SPRN_##exc_lvl_srr0,r9; \ |
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mtspr SPRN_##exc_lvl_srr1,r10; |
|
|
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#if defined(CONFIG_PPC_BOOK3E_MMU) |
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#ifdef CONFIG_PHYS_64BIT |
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#define RESTORE_MAS7 \ |
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lwz r11,MAS7(r1); \ |
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mtspr SPRN_MAS7,r11; |
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#else |
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#define RESTORE_MAS7 |
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#endif /* CONFIG_PHYS_64BIT */ |
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#define RESTORE_MMU_REGS \ |
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lwz r9,MAS0(r1); \ |
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lwz r10,MAS1(r1); \ |
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lwz r11,MAS2(r1); \ |
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mtspr SPRN_MAS0,r9; \ |
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lwz r9,MAS3(r1); \ |
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mtspr SPRN_MAS1,r10; \ |
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lwz r10,MAS6(r1); \ |
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mtspr SPRN_MAS2,r11; \ |
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mtspr SPRN_MAS3,r9; \ |
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mtspr SPRN_MAS6,r10; \ |
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RESTORE_MAS7; |
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#elif defined(CONFIG_44x) |
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#define RESTORE_MMU_REGS \ |
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lwz r9,MMUCR(r1); \ |
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mtspr SPRN_MMUCR,r9; |
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#else |
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#define RESTORE_MMU_REGS |
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#endif |
|
|
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#ifdef CONFIG_40x |
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.globl ret_from_crit_exc |
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ret_from_crit_exc: |
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lis r9,crit_srr0@ha; |
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lwz r9,crit_srr0@l(r9); |
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lis r10,crit_srr1@ha; |
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lwz r10,crit_srr1@l(r10); |
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mtspr SPRN_SRR0,r9; |
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mtspr SPRN_SRR1,r10; |
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RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) |
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_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) |
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#endif /* CONFIG_40x */ |
|
|
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#ifdef CONFIG_BOOKE |
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.globl ret_from_crit_exc |
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ret_from_crit_exc: |
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RESTORE_xSRR(SRR0,SRR1); |
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RESTORE_MMU_REGS; |
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RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI) |
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_ASM_NOKPROBE_SYMBOL(ret_from_crit_exc) |
|
|
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.globl ret_from_debug_exc |
|
ret_from_debug_exc: |
|
RESTORE_xSRR(SRR0,SRR1); |
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RESTORE_xSRR(CSRR0,CSRR1); |
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RESTORE_MMU_REGS; |
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RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI) |
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_ASM_NOKPROBE_SYMBOL(ret_from_debug_exc) |
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|
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.globl ret_from_mcheck_exc |
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ret_from_mcheck_exc: |
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RESTORE_xSRR(SRR0,SRR1); |
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RESTORE_xSRR(CSRR0,CSRR1); |
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RESTORE_xSRR(DSRR0,DSRR1); |
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RESTORE_MMU_REGS; |
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RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI) |
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_ASM_NOKPROBE_SYMBOL(ret_from_mcheck_exc) |
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#endif /* CONFIG_BOOKE */ |
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#endif /* !(CONFIG_4xx || CONFIG_BOOKE) */ |
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|
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/* |
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* PROM code for specific machines follows. Put it |
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* here so it's easy to add arch-specific sections later. |
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* -- Cort |
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*/ |
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#ifdef CONFIG_PPC_RTAS |
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/* |
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* On CHRP, the Run-Time Abstraction Services (RTAS) have to be |
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* called with the MMU off. |
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*/ |
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_GLOBAL(enter_rtas) |
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stwu r1,-INT_FRAME_SIZE(r1) |
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mflr r0 |
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stw r0,INT_FRAME_SIZE+4(r1) |
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LOAD_REG_ADDR(r4, rtas) |
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lis r6,1f@ha /* physical return address for rtas */ |
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addi r6,r6,1f@l |
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tophys(r6,r6) |
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lwz r8,RTASENTRY(r4) |
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lwz r4,RTASBASE(r4) |
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mfmsr r9 |
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stw r9,8(r1) |
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LOAD_REG_IMMEDIATE(r0,MSR_KERNEL) |
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mtmsr r0 /* disable interrupts so SRR0/1 don't get trashed */ |
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li r9,MSR_KERNEL & ~(MSR_IR|MSR_DR) |
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mtlr r6 |
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stw r1, THREAD + RTAS_SP(r2) |
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mtspr SPRN_SRR0,r8 |
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mtspr SPRN_SRR1,r9 |
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rfi |
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1: |
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lis r8, 1f@h |
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ori r8, r8, 1f@l |
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LOAD_REG_IMMEDIATE(r9,MSR_KERNEL) |
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mtspr SPRN_SRR0,r8 |
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mtspr SPRN_SRR1,r9 |
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rfi /* Reactivate MMU translation */ |
|
1: |
|
lwz r8,INT_FRAME_SIZE+4(r1) /* get return address */ |
|
lwz r9,8(r1) /* original msr value */ |
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addi r1,r1,INT_FRAME_SIZE |
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li r0,0 |
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stw r0, THREAD + RTAS_SP(r2) |
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mtlr r8 |
|
mtmsr r9 |
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blr /* return to caller */ |
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_ASM_NOKPROBE_SYMBOL(enter_rtas) |
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#endif /* CONFIG_PPC_RTAS */
|
|
|