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113 lines
3.2 KiB
113 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* common routine and memory layout for Tundra TSI108(Grendel) host bridge |
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* memory controller. |
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* |
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* Author: Jacob Pan ([email protected]) |
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* Alex Bounine ([email protected]) |
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* |
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* Copyright 2004-2006 Freescale Semiconductor, Inc. |
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*/ |
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#ifndef __PPC_KERNEL_TSI108_H |
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#define __PPC_KERNEL_TSI108_H |
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#include <asm/pci-bridge.h> |
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/* Size of entire register space */ |
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#define TSI108_REG_SIZE (0x10000) |
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/* Sizes of register spaces for individual blocks */ |
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#define TSI108_HLP_SIZE 0x1000 |
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#define TSI108_PCI_SIZE 0x1000 |
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#define TSI108_CLK_SIZE 0x1000 |
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#define TSI108_PB_SIZE 0x1000 |
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#define TSI108_SD_SIZE 0x1000 |
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#define TSI108_DMA_SIZE 0x1000 |
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#define TSI108_ETH_SIZE 0x1000 |
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#define TSI108_I2C_SIZE 0x400 |
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#define TSI108_MPIC_SIZE 0x400 |
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#define TSI108_UART0_SIZE 0x200 |
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#define TSI108_GPIO_SIZE 0x200 |
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#define TSI108_UART1_SIZE 0x200 |
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/* Offsets within Tsi108(A) CSR space for individual blocks */ |
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#define TSI108_HLP_OFFSET 0x0000 |
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#define TSI108_PCI_OFFSET 0x1000 |
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#define TSI108_CLK_OFFSET 0x2000 |
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#define TSI108_PB_OFFSET 0x3000 |
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#define TSI108_SD_OFFSET 0x4000 |
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#define TSI108_DMA_OFFSET 0x5000 |
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#define TSI108_ETH_OFFSET 0x6000 |
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#define TSI108_I2C_OFFSET 0x7000 |
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#define TSI108_MPIC_OFFSET 0x7400 |
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#define TSI108_UART0_OFFSET 0x7800 |
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#define TSI108_GPIO_OFFSET 0x7A00 |
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#define TSI108_UART1_OFFSET 0x7C00 |
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/* Tsi108 registers used by common code components */ |
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#define TSI108_PCI_CSR (0x004) |
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#define TSI108_PCI_IRP_CFG_CTL (0x180) |
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#define TSI108_PCI_IRP_STAT (0x184) |
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#define TSI108_PCI_IRP_ENABLE (0x188) |
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#define TSI108_PCI_IRP_INTAD (0x18C) |
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#define TSI108_PCI_IRP_STAT_P_INT (0x00400000) |
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#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000) |
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#define TSI108_CG_PWRUP_STATUS (0x234) |
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#define TSI108_PB_ISR (0x00C) |
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#define TSI108_PB_ERRCS (0x404) |
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#define TSI108_PB_AERR (0x408) |
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#define TSI108_PB_ERRCS_ES (1 << 1) |
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#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8) |
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#define TSI108_PCI_CFG_SIZE (0x01000000) |
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/* |
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* PHY Configuration Options |
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* |
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* Specify "bcm54xx" in the compatible property of your device tree phy |
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* nodes if your board uses the Broadcom PHYs |
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*/ |
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#define TSI108_PHY_MV88E 0 /* Marvel 88Exxxx PHY */ |
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#define TSI108_PHY_BCM54XX 1 /* Broadcom BCM54xx PHY */ |
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/* Global variables */ |
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extern u32 tsi108_pci_cfg_base; |
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/* Exported functions */ |
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extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 val); |
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extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, |
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int offset, int len, u32 * val); |
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extern void tsi108_clear_pci_error(u32 pci_cfg_base); |
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extern phys_addr_t get_csrbase(void); |
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typedef struct { |
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u32 regs; /* hw registers base address */ |
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u32 phyregs; /* phy registers base address */ |
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u16 phy; /* phy address */ |
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u16 irq_num; /* irq number */ |
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u8 mac_addr[6]; /* phy mac address */ |
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u16 phy_type; /* type of phy on board */ |
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} hw_info; |
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extern u32 get_vir_csrbase(void); |
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extern u32 tsi108_csr_vir_base; |
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static inline u32 tsi108_read_reg(u32 reg_offset) |
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{ |
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return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset)); |
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} |
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static inline void tsi108_write_reg(u32 reg_offset, u32 val) |
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{ |
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out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val); |
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} |
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#endif /* __PPC_KERNEL_TSI108_H */
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