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181 lines
4.9 KiB
181 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* Copyright (C) 2004 Paul Mackerras <[email protected]>, IBM |
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*/ |
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#include <asm/inst.h> |
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struct pt_regs; |
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/* |
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* We don't allow single-stepping an mtmsrd that would clear |
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* MSR_RI, since that would make the exception unrecoverable. |
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* Since we need to single-step to proceed from a breakpoint, |
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* we don't allow putting a breakpoint on an mtmsrd instruction. |
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* Similarly we don't allow breakpoints on rfid instructions. |
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* These macros tell us if an instruction is a mtmsrd or rfid. |
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* Note that these return true for both mtmsr/rfi (32-bit) |
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* and mtmsrd/rfid (64-bit). |
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*/ |
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#define IS_MTMSRD(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124) |
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#define IS_RFID(instr) ((ppc_inst_val(instr) & 0xfc0007be) == 0x4c000024) |
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enum instruction_type { |
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COMPUTE, /* arith/logical/CR op, etc. */ |
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LOAD, /* load and store types need to be contiguous */ |
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LOAD_MULTI, |
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LOAD_FP, |
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LOAD_VMX, |
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LOAD_VSX, |
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STORE, |
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STORE_MULTI, |
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STORE_FP, |
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STORE_VMX, |
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STORE_VSX, |
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LARX, |
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STCX, |
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BRANCH, |
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MFSPR, |
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MTSPR, |
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CACHEOP, |
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BARRIER, |
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SYSCALL, |
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SYSCALL_VECTORED_0, |
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MFMSR, |
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MTMSR, |
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RFI, |
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INTERRUPT, |
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UNKNOWN |
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}; |
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#define INSTR_TYPE_MASK 0x1f |
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#define OP_IS_LOAD(type) ((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX) |
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#define OP_IS_STORE(type) ((STORE <= (type) && (type) <= STORE_VSX) || (type) == STCX) |
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#define OP_IS_LOAD_STORE(type) (LOAD <= (type) && (type) <= STCX) |
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/* Compute flags, ORed in with type */ |
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#define SETREG 0x20 |
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#define SETCC 0x40 |
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#define SETXER 0x80 |
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/* Branch flags, ORed in with type */ |
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#define SETLK 0x20 |
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#define BRTAKEN 0x40 |
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#define DECCTR 0x80 |
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/* Load/store flags, ORed in with type */ |
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#define SIGNEXT 0x20 |
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#define UPDATE 0x40 /* matches bit in opcode 31 instructions */ |
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#define BYTEREV 0x80 |
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#define FPCONV 0x100 |
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/* Barrier type field, ORed in with type */ |
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#define BARRIER_MASK 0xe0 |
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#define BARRIER_SYNC 0x00 |
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#define BARRIER_ISYNC 0x20 |
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#define BARRIER_EIEIO 0x40 |
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#define BARRIER_LWSYNC 0x60 |
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#define BARRIER_PTESYNC 0x80 |
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/* Cacheop values, ORed in with type */ |
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#define CACHEOP_MASK 0x700 |
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#define DCBST 0 |
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#define DCBF 0x100 |
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#define DCBTST 0x200 |
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#define DCBT 0x300 |
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#define ICBI 0x400 |
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#define DCBZ 0x500 |
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/* VSX flags values */ |
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#define VSX_FPCONV 1 /* do floating point SP/DP conversion */ |
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#define VSX_SPLAT 2 /* store loaded value into all elements */ |
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#define VSX_LDLEFT 4 /* load VSX register from left */ |
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#define VSX_CHECK_VEC 8 /* check MSR_VEC not MSR_VSX for reg >= 32 */ |
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/* Prefixed flag, ORed in with type */ |
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#define PREFIXED 0x800 |
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/* Size field in type word */ |
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#define SIZE(n) ((n) << 12) |
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#define GETSIZE(w) ((w) >> 12) |
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#define GETTYPE(t) ((t) & INSTR_TYPE_MASK) |
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#define GETLENGTH(t) (((t) & PREFIXED) ? 8 : 4) |
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#define MKOP(t, f, s) ((t) | (f) | SIZE(s)) |
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/* Prefix instruction operands */ |
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#define GET_PREFIX_RA(i) (((i) >> 16) & 0x1f) |
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#define GET_PREFIX_R(i) ((i) & (1ul << 20)) |
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extern s32 patch__exec_instr; |
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struct instruction_op { |
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int type; |
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int reg; |
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unsigned long val; |
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/* For LOAD/STORE/LARX/STCX */ |
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unsigned long ea; |
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int update_reg; |
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/* For MFSPR */ |
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int spr; |
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u32 ccval; |
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u32 xerval; |
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u8 element_size; /* for VSX/VMX loads/stores */ |
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u8 vsx_flags; |
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}; |
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union vsx_reg { |
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u8 b[16]; |
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u16 h[8]; |
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u32 w[4]; |
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unsigned long d[2]; |
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float fp[4]; |
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double dp[2]; |
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__vector128 v; |
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}; |
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/* |
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* Decode an instruction, and return information about it in *op |
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* without changing *regs. |
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* |
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* Return value is 1 if the instruction can be emulated just by |
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* updating *regs with the information in *op, -1 if we need the |
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* GPRs but *regs doesn't contain the full register set, or 0 |
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* otherwise. |
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*/ |
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extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs, |
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struct ppc_inst instr); |
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/* |
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* Emulate an instruction that can be executed just by updating |
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* fields in *regs. |
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*/ |
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void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op); |
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/* |
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* Emulate instructions that cause a transfer of control, |
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* arithmetic/logical instructions, loads and stores, |
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* cache operations and barriers. |
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* |
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* Returns 1 if the instruction was emulated successfully, |
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* 0 if it could not be emulated, or -1 for an instruction that |
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* should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.). |
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*/ |
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extern int emulate_step(struct pt_regs *regs, struct ppc_inst instr); |
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/* |
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* Emulate a load or store instruction by reading/writing the |
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* memory of the current process. FP/VMX/VSX registers are assumed |
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* to hold live values if the appropriate enable bit in regs->msr is |
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* set; otherwise this will use the saved values in the thread struct |
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* for user-mode accesses. |
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*/ |
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extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op); |
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extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg, |
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const void *mem, bool cross_endian); |
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extern void emulate_vsx_store(struct instruction_op *op, |
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const union vsx_reg *reg, void *mem, |
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bool cross_endian); |
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extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);
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