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694 lines
19 KiB
694 lines
19 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _SMU_H |
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#define _SMU_H |
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|
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/* |
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* Definitions for talking to the SMU chip in newer G5 PowerMacs |
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*/ |
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#ifdef __KERNEL__ |
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#include <linux/list.h> |
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#endif |
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#include <linux/types.h> |
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|
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/* |
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* Known SMU commands |
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* |
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* Most of what is below comes from looking at the Open Firmware driver, |
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* though this is still incomplete and could use better documentation here |
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* or there... |
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*/ |
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/* |
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* Partition info commands |
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* |
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* These commands are used to retrieve the sdb-partition-XX datas from |
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* the SMU. The length is always 2. First byte is the subcommand code |
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* and second byte is the partition ID. |
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* |
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* The reply is 6 bytes: |
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* |
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* - 0..1 : partition address |
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* - 2 : a byte containing the partition ID |
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* - 3 : length (maybe other bits are rest of header ?) |
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* |
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* The data must then be obtained with calls to another command: |
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* SMU_CMD_MISC_ee_GET_DATABLOCK_REC (described below). |
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*/ |
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#define SMU_CMD_PARTITION_COMMAND 0x3e |
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#define SMU_CMD_PARTITION_LATEST 0x01 |
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#define SMU_CMD_PARTITION_BASE 0x02 |
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#define SMU_CMD_PARTITION_UPDATE 0x03 |
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/* |
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* Fan control |
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* |
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* This is a "mux" for fan control commands. The command seem to |
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* act differently based on the number of arguments. With 1 byte |
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* of argument, this seem to be queries for fans status, setpoint, |
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* etc..., while with 0xe arguments, we will set the fans speeds. |
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* |
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* Queries (1 byte arg): |
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* --------------------- |
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* |
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* arg=0x01: read RPM fans status |
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* arg=0x02: read RPM fans setpoint |
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* arg=0x11: read PWM fans status |
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* arg=0x12: read PWM fans setpoint |
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* |
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* the "status" queries return the current speed while the "setpoint" ones |
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* return the programmed/target speed. It _seems_ that the result is a bit |
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* mask in the first byte of active/available fans, followed by 6 words (16 |
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* bits) containing the requested speed. |
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* |
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* Setpoint (14 bytes arg): |
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* ------------------------ |
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* |
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* first arg byte is 0 for RPM fans and 0x10 for PWM. Second arg byte is the |
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* mask of fans affected by the command. Followed by 6 words containing the |
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* setpoint value for selected fans in the mask (or 0 if mask value is 0) |
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*/ |
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#define SMU_CMD_FAN_COMMAND 0x4a |
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/* |
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* Battery access |
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* |
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* Same command number as the PMU, could it be same syntax ? |
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*/ |
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#define SMU_CMD_BATTERY_COMMAND 0x6f |
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#define SMU_CMD_GET_BATTERY_INFO 0x00 |
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|
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/* |
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* Real time clock control |
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* |
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* This is a "mux", first data byte contains the "sub" command. |
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* The "RTC" part of the SMU controls the date, time, powerup |
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* timer, but also a PRAM |
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* |
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* Dates are in BCD format on 7 bytes: |
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* [sec] [min] [hour] [weekday] [month day] [month] [year] |
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* with month being 1 based and year minus 100 |
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*/ |
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#define SMU_CMD_RTC_COMMAND 0x8e |
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#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */ |
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#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */ |
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#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02 |
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#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */ |
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#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */ |
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#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */ |
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#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */ |
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#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */ |
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#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */ |
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#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */ |
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#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */ |
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#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */ |
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/* |
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* i2c commands |
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* |
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* To issue an i2c command, first is to send a parameter block to |
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* the SMU. This is a command of type 0x9a with 9 bytes of header |
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* eventually followed by data for a write: |
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* |
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* 0: bus number (from device-tree usually, SMU has lots of busses !) |
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* 1: transfer type/format (see below) |
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* 2: device address. For combined and combined4 type transfers, this |
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* is the "write" version of the address (bit 0x01 cleared) |
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* 3: subaddress length (0..3) |
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* 4: subaddress byte 0 (or only byte for subaddress length 1) |
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* 5: subaddress byte 1 |
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* 6: subaddress byte 2 |
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* 7: combined address (device address for combined mode data phase) |
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* 8: data length |
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* |
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* The transfer types are the same good old Apple ones it seems, |
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* that is: |
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* - 0x00: Simple transfer |
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* - 0x01: Subaddress transfer (addr write + data tx, no restart) |
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* - 0x02: Combined transfer (addr write + restart + data tx) |
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* |
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* This is then followed by actual data for a write. |
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* |
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* At this point, the OF driver seems to have a limitation on transfer |
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* sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know |
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* whether this is just an OF limit due to some temporary buffer size |
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* or if this is an SMU imposed limit. This driver has the same limitation |
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* for now as I use a 0x10 bytes temporary buffer as well |
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* |
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* Once that is completed, a response is expected from the SMU. This is |
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* obtained via a command of type 0x9a with a length of 1 byte containing |
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* 0 as the data byte. OF also fills the rest of the data buffer with 0xff's |
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* though I can't tell yet if this is actually necessary. Once this command |
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* is complete, at this point, all I can tell is what OF does. OF tests |
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* byte 0 of the reply: |
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* - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ? |
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* - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0) |
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* - on write, < 0 -> failure (immediate exit) |
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* - else, OF just exists (without error, weird) |
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* |
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* So on read, there is this wait-for-busy thing when getting a 0xfc or |
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* 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and |
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* doing the above again until either the retries expire or the result |
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* is no longer 0xfe or 0xfc |
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* |
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* The Darwin I2C driver is less subtle though. On any non-success status |
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* from the response command, it waits 5ms and tries again up to 20 times, |
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* it doesn't differentiate between fatal errors or "busy" status. |
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* |
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* This driver provides an asynchronous paramblock based i2c command |
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* interface to be used either directly by low level code or by a higher |
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* level driver interfacing to the linux i2c layer. The current |
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* implementation of this relies on working timers & timer interrupts |
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* though, so be careful of calling context for now. This may be "fixed" |
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* in the future by adding a polling facility. |
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*/ |
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#define SMU_CMD_I2C_COMMAND 0x9a |
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/* transfer types */ |
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#define SMU_I2C_TRANSFER_SIMPLE 0x00 |
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#define SMU_I2C_TRANSFER_STDSUB 0x01 |
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#define SMU_I2C_TRANSFER_COMBINED 0x02 |
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/* |
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* Power supply control |
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* |
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* The "sub" command is an ASCII string in the data, the |
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* data length is that of the string. |
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* |
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* The VSLEW command can be used to get or set the voltage slewing. |
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* - length 5 (only "VSLEW") : it returns "DONE" and 3 bytes of |
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* reply at data offset 6, 7 and 8. |
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* - length 8 ("VSLEWxyz") has 3 additional bytes appended, and is |
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* used to set the voltage slewing point. The SMU replies with "DONE" |
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* I yet have to figure out their exact meaning of those 3 bytes in |
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* both cases. They seem to be: |
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* x = processor mask |
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* y = op. point index |
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* z = processor freq. step index |
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* I haven't yet deciphered result codes |
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* |
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*/ |
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#define SMU_CMD_POWER_COMMAND 0xaa |
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#define SMU_CMD_POWER_RESTART "RESTART" |
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#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN" |
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#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW" |
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/* |
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* Read ADC sensors |
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* |
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* This command takes one byte of parameter: the sensor ID (or "reg" |
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* value in the device-tree) and returns a 16 bits value |
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*/ |
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#define SMU_CMD_READ_ADC 0xd8 |
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/* Misc commands |
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* |
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* This command seem to be a grab bag of various things |
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* |
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* Parameters: |
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* 1: subcommand |
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*/ |
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#define SMU_CMD_MISC_df_COMMAND 0xdf |
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/* |
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* Sets "system ready" status |
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* |
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* I did not yet understand how it exactly works or what it does. |
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* |
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* Guessing from OF code, 0x02 activates the display backlight. Apple uses/used |
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* the same codebase for all OF versions. On PowerBooks, this command would |
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* enable the backlight. For the G5s, it only activates the front LED. However, |
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* don't take this for granted. |
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* |
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* Parameters: |
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* 2: status [0x00, 0x01 or 0x02] |
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*/ |
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#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 |
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/* |
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* Sets mode of power switch. |
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* |
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* What this actually does is not yet known. Maybe it enables some interrupt. |
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* |
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* Parameters: |
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* 2: enable power switch? [0x00 or 0x01] |
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* 3 (optional): enable nmi? [0x00 or 0x01] |
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* |
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* Returns: |
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* If parameter 2 is 0x00 and parameter 3 is not specified, returns whether |
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* NMI is enabled. Otherwise unknown. |
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*/ |
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#define SMU_CMD_MISC_df_NMI_OPTION 0x04 |
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/* Sets LED dimm offset. |
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* |
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* The front LED dimms itself during sleep. Its brightness (or, well, the PWM |
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* frequency) depends on current time. Therefore, the SMU needs to know the |
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* timezone. |
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* |
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* Parameters: |
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* 2-8: unknown (BCD coding) |
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*/ |
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#define SMU_CMD_MISC_df_DIMM_OFFSET 0x99 |
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/* |
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* Version info commands |
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* |
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* Parameters: |
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* 1 (optional): Specifies version part to retrieve |
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* |
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* Returns: |
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* Version value |
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*/ |
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#define SMU_CMD_VERSION_COMMAND 0xea |
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#define SMU_VERSION_RUNNING 0x00 |
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#define SMU_VERSION_BASE 0x01 |
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#define SMU_VERSION_UPDATE 0x02 |
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/* |
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* Switches |
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* |
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* These are switches whose status seems to be known to the SMU. |
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* |
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* Parameters: |
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* none |
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* |
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* Result: |
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* Switch bits (ORed, see below) |
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*/ |
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#define SMU_CMD_SWITCHES 0xdc |
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/* Switches bits */ |
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#define SMU_SWITCH_CASE_CLOSED 0x01 |
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#define SMU_SWITCH_AC_POWER 0x04 |
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#define SMU_SWITCH_POWER_SWITCH 0x08 |
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/* |
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* Misc commands |
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* |
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* This command seem to be a grab bag of various things |
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* |
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* SMU_CMD_MISC_ee_GET_DATABLOCK_REC is used, among others, to |
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* transfer blocks of data from the SMU. So far, I've decrypted it's |
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* usage to retrieve partition data. In order to do that, you have to |
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* break your transfer in "chunks" since that command cannot transfer |
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* more than a chunk at a time. The chunk size used by OF is 0xe bytes, |
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* but it seems that the darwin driver will let you do 0x1e bytes if |
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* your "PMU" version is >= 0x30. You can get the "PMU" version apparently |
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* either in the last 16 bits of property "smu-version-pmu" or as the 16 |
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* bytes at offset 1 of "smu-version-info" |
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* |
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* For each chunk, the command takes 7 bytes of arguments: |
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* byte 0: subcommand code (0x02) |
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* byte 1: 0x04 (always, I don't know what it means, maybe the address |
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* space to use or some other nicety. It's hard coded in OF) |
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* byte 2..5: SMU address of the chunk (big endian 32 bits) |
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* byte 6: size to transfer (up to max chunk size) |
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* |
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* The data is returned directly |
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*/ |
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#define SMU_CMD_MISC_ee_COMMAND 0xee |
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#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02 |
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/* Retrieves currently used watts. |
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* |
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* Parameters: |
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* 1: 0x03 (Meaning unknown) |
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*/ |
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#define SMU_CMD_MISC_ee_GET_WATTS 0x03 |
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#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */ |
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#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */ |
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/* |
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* Power related commands |
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* |
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* Parameters: |
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* 1: subcommand |
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*/ |
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#define SMU_CMD_POWER_EVENTS_COMMAND 0x8f |
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/* SMU_POWER_EVENTS subcommands */ |
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enum { |
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SMU_PWR_GET_POWERUP_EVENTS = 0x00, |
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SMU_PWR_SET_POWERUP_EVENTS = 0x01, |
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SMU_PWR_CLR_POWERUP_EVENTS = 0x02, |
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SMU_PWR_GET_WAKEUP_EVENTS = 0x03, |
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SMU_PWR_SET_WAKEUP_EVENTS = 0x04, |
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SMU_PWR_CLR_WAKEUP_EVENTS = 0x05, |
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/* |
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* Get last shutdown cause |
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* |
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* Returns: |
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* 1 byte (signed char): Last shutdown cause. Exact meaning unknown. |
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*/ |
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SMU_PWR_LAST_SHUTDOWN_CAUSE = 0x07, |
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/* |
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* Sets or gets server ID. Meaning or use is unknown. |
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* |
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* Parameters: |
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* 2 (optional): Set server ID (1 byte) |
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* |
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* Returns: |
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* 1 byte (server ID?) |
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*/ |
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SMU_PWR_SERVER_ID = 0x08, |
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}; |
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/* Power events wakeup bits */ |
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enum { |
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SMU_PWR_WAKEUP_KEY = 0x01, /* Wake on key press */ |
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SMU_PWR_WAKEUP_AC_INSERT = 0x02, /* Wake on AC adapter plug */ |
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SMU_PWR_WAKEUP_AC_CHANGE = 0x04, |
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SMU_PWR_WAKEUP_LID_OPEN = 0x08, |
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SMU_PWR_WAKEUP_RING = 0x10, |
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}; |
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/* |
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* - Kernel side interface - |
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*/ |
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#ifdef __KERNEL__ |
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/* |
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* Asynchronous SMU commands |
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* |
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* Fill up this structure and submit it via smu_queue_command(), |
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* and get notified by the optional done() callback, or because |
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* status becomes != 1 |
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*/ |
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struct smu_cmd; |
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struct smu_cmd |
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{ |
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/* public */ |
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u8 cmd; /* command */ |
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int data_len; /* data len */ |
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int reply_len; /* reply len */ |
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void *data_buf; /* data buffer */ |
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void *reply_buf; /* reply buffer */ |
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int status; /* command status */ |
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void (*done)(struct smu_cmd *cmd, void *misc); |
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void *misc; |
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/* private */ |
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struct list_head link; |
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}; |
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/* |
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* Queues an SMU command, all fields have to be initialized |
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*/ |
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extern int smu_queue_cmd(struct smu_cmd *cmd); |
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/* |
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* Simple command wrapper. This structure embeds a small buffer |
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* to ease sending simple SMU commands from the stack |
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*/ |
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struct smu_simple_cmd |
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{ |
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struct smu_cmd cmd; |
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u8 buffer[16]; |
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}; |
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/* |
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* Queues a simple command. All fields will be initialized by that |
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* function |
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*/ |
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extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command, |
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unsigned int data_len, |
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void (*done)(struct smu_cmd *cmd, void *misc), |
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void *misc, |
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...); |
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/* |
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* Completion helper. Pass it to smu_queue_simple or as 'done' |
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* member to smu_queue_cmd, it will call complete() on the struct |
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* completion passed in the "misc" argument |
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*/ |
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extern void smu_done_complete(struct smu_cmd *cmd, void *misc); |
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/* |
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* Synchronous helpers. Will spin-wait for completion of a command |
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*/ |
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extern void smu_spinwait_cmd(struct smu_cmd *cmd); |
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static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd) |
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{ |
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smu_spinwait_cmd(&scmd->cmd); |
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} |
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/* |
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* Poll routine to call if blocked with irqs off |
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*/ |
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extern void smu_poll(void); |
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/* |
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* Init routine, presence check.... |
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*/ |
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extern int smu_init(void); |
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extern int smu_present(void); |
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struct platform_device; |
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extern struct platform_device *smu_get_ofdev(void); |
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/* |
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* Common command wrappers |
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*/ |
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extern void smu_shutdown(void); |
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extern void smu_restart(void); |
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struct rtc_time; |
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extern int smu_get_rtc_time(struct rtc_time *time, int spinwait); |
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extern int smu_set_rtc_time(struct rtc_time *time, int spinwait); |
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/* |
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* Kernel asynchronous i2c interface |
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*/ |
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#define SMU_I2C_READ_MAX 0x1d |
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#define SMU_I2C_WRITE_MAX 0x15 |
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/* SMU i2c header, exactly matches i2c header on wire */ |
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struct smu_i2c_param |
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{ |
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u8 bus; /* SMU bus ID (from device tree) */ |
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u8 type; /* i2c transfer type */ |
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u8 devaddr; /* device address (includes direction) */ |
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u8 sublen; /* subaddress length */ |
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u8 subaddr[3]; /* subaddress */ |
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u8 caddr; /* combined address, filled by SMU driver */ |
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u8 datalen; /* length of transfer */ |
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u8 data[SMU_I2C_READ_MAX]; /* data */ |
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}; |
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struct smu_i2c_cmd |
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{ |
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/* public */ |
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struct smu_i2c_param info; |
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void (*done)(struct smu_i2c_cmd *cmd, void *misc); |
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void *misc; |
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int status; /* 1 = pending, 0 = ok, <0 = fail */ |
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/* private */ |
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struct smu_cmd scmd; |
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int read; |
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int stage; |
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int retries; |
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u8 pdata[32]; |
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struct list_head link; |
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}; |
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/* |
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* Call this to queue an i2c command to the SMU. You must fill info, |
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* including info.data for a write, done and misc. |
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* For now, no polling interface is provided so you have to use completion |
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* callback. |
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*/ |
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extern int smu_queue_i2c(struct smu_i2c_cmd *cmd); |
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#endif /* __KERNEL__ */ |
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/* |
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* - SMU "sdb" partitions informations - |
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*/ |
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/* |
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* Partition header format |
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*/ |
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struct smu_sdbp_header { |
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__u8 id; |
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__u8 len; |
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__u8 version; |
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__u8 flags; |
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}; |
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/* |
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* demangle 16 and 32 bits integer in some SMU partitions |
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* (currently, afaik, this concerns only the FVT partition |
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* (0x12) |
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*/ |
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#define SMU_U16_MIX(x) le16_to_cpu(x) |
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#define SMU_U32_MIX(x) ((((x) & 0xff00ff00u) >> 8)|(((x) & 0x00ff00ffu) << 8)) |
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/* This is the definition of the SMU sdb-partition-0x12 table (called |
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* CPU F/V/T operating points in Darwin). The definition for all those |
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* SMU tables should be moved to some separate file |
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*/ |
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#define SMU_SDB_FVT_ID 0x12 |
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struct smu_sdbp_fvt { |
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__u32 sysclk; /* Base SysClk frequency in Hz for |
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* this operating point. Value need to |
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* be unmixed with SMU_U32_MIX() |
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*/ |
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__u8 pad; |
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__u8 maxtemp; /* Max temp. supported by this |
|
* operating point |
|
*/ |
|
|
|
__u16 volts[3]; /* CPU core voltage for the 3 |
|
* PowerTune modes, a mode with |
|
* 0V = not supported. Value need |
|
* to be unmixed with SMU_U16_MIX() |
|
*/ |
|
}; |
|
|
|
/* This partition contains voltage & current sensor calibration |
|
* informations |
|
*/ |
|
#define SMU_SDB_CPUVCP_ID 0x21 |
|
|
|
struct smu_sdbp_cpuvcp { |
|
__u16 volt_scale; /* u4.12 fixed point */ |
|
__s16 volt_offset; /* s4.12 fixed point */ |
|
__u16 curr_scale; /* u4.12 fixed point */ |
|
__s16 curr_offset; /* s4.12 fixed point */ |
|
__s32 power_quads[3]; /* s4.28 fixed point */ |
|
}; |
|
|
|
/* This partition contains CPU thermal diode calibration |
|
*/ |
|
#define SMU_SDB_CPUDIODE_ID 0x18 |
|
|
|
struct smu_sdbp_cpudiode { |
|
__u16 m_value; /* u1.15 fixed point */ |
|
__s16 b_value; /* s10.6 fixed point */ |
|
|
|
}; |
|
|
|
/* This partition contains Slots power calibration |
|
*/ |
|
#define SMU_SDB_SLOTSPOW_ID 0x78 |
|
|
|
struct smu_sdbp_slotspow { |
|
__u16 pow_scale; /* u4.12 fixed point */ |
|
__s16 pow_offset; /* s4.12 fixed point */ |
|
}; |
|
|
|
/* This partition contains machine specific version information about |
|
* the sensor/control layout |
|
*/ |
|
#define SMU_SDB_SENSORTREE_ID 0x25 |
|
|
|
struct smu_sdbp_sensortree { |
|
__u8 model_id; |
|
__u8 unknown[3]; |
|
}; |
|
|
|
/* This partition contains CPU thermal control PID informations. So far |
|
* only single CPU machines have been seen with an SMU, so we assume this |
|
* carries only informations for those |
|
*/ |
|
#define SMU_SDB_CPUPIDDATA_ID 0x17 |
|
|
|
struct smu_sdbp_cpupiddata { |
|
__u8 unknown1; |
|
__u8 target_temp_delta; |
|
__u8 unknown2; |
|
__u8 history_len; |
|
__s16 power_adj; |
|
__u16 max_power; |
|
__s32 gp,gr,gd; |
|
}; |
|
|
|
|
|
/* Other partitions without known structures */ |
|
#define SMU_SDB_DEBUG_SWITCHES_ID 0x05 |
|
|
|
#ifdef __KERNEL__ |
|
/* |
|
* This returns the pointer to an SMU "sdb" partition data or NULL |
|
* if not found. The data format is described below |
|
*/ |
|
extern const struct smu_sdbp_header *smu_get_sdb_partition(int id, |
|
unsigned int *size); |
|
|
|
/* Get "sdb" partition data from an SMU satellite */ |
|
extern struct smu_sdbp_header *smu_sat_get_sdb_partition(unsigned int sat_id, |
|
int id, unsigned int *size); |
|
|
|
|
|
#endif /* __KERNEL__ */ |
|
|
|
|
|
/* |
|
* - Userland interface - |
|
*/ |
|
|
|
/* |
|
* A given instance of the device can be configured for 2 different |
|
* things at the moment: |
|
* |
|
* - sending SMU commands (default at open() time) |
|
* - receiving SMU events (not yet implemented) |
|
* |
|
* Commands are written with write() of a command block. They can be |
|
* "driver" commands (for example to switch to event reception mode) |
|
* or real SMU commands. They are made of a header followed by command |
|
* data if any. |
|
* |
|
* For SMU commands (not for driver commands), you can then read() back |
|
* a reply. The reader will be blocked or not depending on how the device |
|
* file is opened. poll() isn't implemented yet. The reply will consist |
|
* of a header as well, followed by the reply data if any. You should |
|
* always provide a buffer large enough for the maximum reply data, I |
|
* recommand one page. |
|
* |
|
* It is illegal to send SMU commands through a file descriptor configured |
|
* for events reception |
|
* |
|
*/ |
|
struct smu_user_cmd_hdr |
|
{ |
|
__u32 cmdtype; |
|
#define SMU_CMDTYPE_SMU 0 /* SMU command */ |
|
#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */ |
|
#define SMU_CMDTYPE_GET_PARTITION 2 /* retrieve an sdb partition */ |
|
|
|
__u8 cmd; /* SMU command byte */ |
|
__u8 pad[3]; /* padding */ |
|
__u32 data_len; /* Length of data following */ |
|
}; |
|
|
|
struct smu_user_reply_hdr |
|
{ |
|
__u32 status; /* Command status */ |
|
__u32 reply_len; /* Length of data follwing */ |
|
}; |
|
|
|
#endif /* _SMU_H */
|
|
|