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790 lines
20 KiB
790 lines
20 KiB
/* |
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* Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. |
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*/ |
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#ifndef _ASM_POWERPC_PPC_ASM_H |
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#define _ASM_POWERPC_PPC_ASM_H |
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#include <linux/stringify.h> |
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#include <asm/asm-compat.h> |
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#include <asm/processor.h> |
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#include <asm/ppc-opcode.h> |
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#include <asm/firmware.h> |
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#include <asm/feature-fixups.h> |
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#ifdef __ASSEMBLY__ |
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#define SZL (BITS_PER_LONG/8) |
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/* |
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* Macros for storing registers into and loading registers from |
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* exception frames. |
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*/ |
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#ifdef __powerpc64__ |
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#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base) |
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#define REST_GPR(n, base) ld n,GPR0+8*(n)(base) |
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#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) |
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#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) |
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#else |
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#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) |
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#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) |
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#define SAVE_NVGPRS(base) stmw 13, GPR0+4*13(base) |
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#define REST_NVGPRS(base) lmw 13, GPR0+4*13(base) |
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#endif |
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#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) |
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#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) |
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#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) |
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#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) |
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#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) |
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#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) |
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#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) |
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#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) |
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#define SAVE_FPR(n, base) stfd n,8*TS_FPRWIDTH*(n)(base) |
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#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) |
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#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) |
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#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) |
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#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) |
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#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) |
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#define REST_FPR(n, base) lfd n,8*TS_FPRWIDTH*(n)(base) |
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#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) |
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#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) |
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#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) |
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#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) |
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#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) |
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#define SAVE_VR(n,b,base) li b,16*(n); stvx n,base,b |
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#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) |
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#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base) |
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#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base) |
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#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base) |
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#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base) |
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#define REST_VR(n,b,base) li b,16*(n); lvx n,base,b |
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#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) |
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#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base) |
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#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base) |
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#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base) |
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#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base) |
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#ifdef __BIG_ENDIAN__ |
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#define STXVD2X_ROT(n,b,base) STXVD2X(n,b,base) |
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#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base) |
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#else |
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#define STXVD2X_ROT(n,b,base) XXSWAPD(n,n); \ |
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STXVD2X(n,b,base); \ |
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XXSWAPD(n,n) |
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#define LXVD2X_ROT(n,b,base) LXVD2X(n,b,base); \ |
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XXSWAPD(n,n) |
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#endif |
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/* Save the lower 32 VSRs in the thread VSR region */ |
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#define SAVE_VSR(n,b,base) li b,16*(n); STXVD2X_ROT(n,R##base,R##b) |
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#define SAVE_2VSRS(n,b,base) SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base) |
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#define SAVE_4VSRS(n,b,base) SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base) |
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#define SAVE_8VSRS(n,b,base) SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base) |
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#define SAVE_16VSRS(n,b,base) SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base) |
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#define SAVE_32VSRS(n,b,base) SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base) |
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#define REST_VSR(n,b,base) li b,16*(n); LXVD2X_ROT(n,R##base,R##b) |
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#define REST_2VSRS(n,b,base) REST_VSR(n,b,base); REST_VSR(n+1,b,base) |
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#define REST_4VSRS(n,b,base) REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base) |
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#define REST_8VSRS(n,b,base) REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base) |
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#define REST_16VSRS(n,b,base) REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base) |
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#define REST_32VSRS(n,b,base) REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base) |
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/* |
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* b = base register for addressing, o = base offset from register of 1st EVR |
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* n = first EVR, s = scratch |
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*/ |
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#define SAVE_EVR(n,s,b,o) evmergehi s,s,n; stw s,o+4*(n)(b) |
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#define SAVE_2EVRS(n,s,b,o) SAVE_EVR(n,s,b,o); SAVE_EVR(n+1,s,b,o) |
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#define SAVE_4EVRS(n,s,b,o) SAVE_2EVRS(n,s,b,o); SAVE_2EVRS(n+2,s,b,o) |
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#define SAVE_8EVRS(n,s,b,o) SAVE_4EVRS(n,s,b,o); SAVE_4EVRS(n+4,s,b,o) |
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#define SAVE_16EVRS(n,s,b,o) SAVE_8EVRS(n,s,b,o); SAVE_8EVRS(n+8,s,b,o) |
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#define SAVE_32EVRS(n,s,b,o) SAVE_16EVRS(n,s,b,o); SAVE_16EVRS(n+16,s,b,o) |
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#define REST_EVR(n,s,b,o) lwz s,o+4*(n)(b); evmergelo n,s,n |
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#define REST_2EVRS(n,s,b,o) REST_EVR(n,s,b,o); REST_EVR(n+1,s,b,o) |
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#define REST_4EVRS(n,s,b,o) REST_2EVRS(n,s,b,o); REST_2EVRS(n+2,s,b,o) |
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#define REST_8EVRS(n,s,b,o) REST_4EVRS(n,s,b,o); REST_4EVRS(n+4,s,b,o) |
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#define REST_16EVRS(n,s,b,o) REST_8EVRS(n,s,b,o); REST_8EVRS(n+8,s,b,o) |
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#define REST_32EVRS(n,s,b,o) REST_16EVRS(n,s,b,o); REST_16EVRS(n+16,s,b,o) |
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/* Macros to adjust thread priority for hardware multithreading */ |
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#define HMT_VERY_LOW or 31,31,31 # very low priority |
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#define HMT_LOW or 1,1,1 |
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#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority |
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#define HMT_MEDIUM or 2,2,2 |
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#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority |
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#define HMT_HIGH or 3,3,3 |
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#define HMT_EXTRA_HIGH or 7,7,7 # power7 only |
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#ifdef CONFIG_PPC64 |
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#define ULONG_SIZE 8 |
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#else |
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#define ULONG_SIZE 4 |
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#endif |
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#define __VCPU_GPR(n) (VCPU_GPRS + (n * ULONG_SIZE)) |
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#define VCPU_GPR(n) __VCPU_GPR(__REG_##n) |
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#ifdef __KERNEL__ |
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/* |
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* We use __powerpc64__ here because we want the compat VDSO to use the 32-bit |
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* version below in the else case of the ifdef. |
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*/ |
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#ifdef __powerpc64__ |
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#define STACKFRAMESIZE 256 |
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#define __STK_REG(i) (112 + ((i)-14)*8) |
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#define STK_REG(i) __STK_REG(__REG_##i) |
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#ifdef PPC64_ELF_ABI_v2 |
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#define STK_GOT 24 |
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#define __STK_PARAM(i) (32 + ((i)-3)*8) |
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#else |
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#define STK_GOT 40 |
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#define __STK_PARAM(i) (48 + ((i)-3)*8) |
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#endif |
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#define STK_PARAM(i) __STK_PARAM(__REG_##i) |
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#ifdef PPC64_ELF_ABI_v2 |
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#define _GLOBAL(name) \ |
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.align 2 ; \ |
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.type name,@function; \ |
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.globl name; \ |
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name: |
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#define _GLOBAL_TOC(name) \ |
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.align 2 ; \ |
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.type name,@function; \ |
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.globl name; \ |
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name: \ |
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0: addis r2,r12,(.TOC.-0b)@ha; \ |
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addi r2,r2,(.TOC.-0b)@l; \ |
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.localentry name,.-name |
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#define DOTSYM(a) a |
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#else |
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#define XGLUE(a,b) a##b |
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#define GLUE(a,b) XGLUE(a,b) |
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#define _GLOBAL(name) \ |
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.align 2 ; \ |
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.globl name; \ |
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.globl GLUE(.,name); \ |
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.pushsection ".opd","aw"; \ |
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name: \ |
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.quad GLUE(.,name); \ |
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.quad .TOC.@tocbase; \ |
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.quad 0; \ |
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.popsection; \ |
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.type GLUE(.,name),@function; \ |
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GLUE(.,name): |
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#define _GLOBAL_TOC(name) _GLOBAL(name) |
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#define DOTSYM(a) GLUE(.,a) |
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#endif |
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#else /* 32-bit */ |
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#define _ENTRY(n) \ |
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.globl n; \ |
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n: |
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#define _GLOBAL(n) \ |
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.stabs __stringify(n:F-1),N_FUN,0,0,n;\ |
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.globl n; \ |
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n: |
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#define _GLOBAL_TOC(name) _GLOBAL(name) |
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#define DOTSYM(a) a |
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#endif |
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/* |
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* __kprobes (the C annotation) puts the symbol into the .kprobes.text |
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* section, which gets emitted at the end of regular text. |
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* |
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* _ASM_NOKPROBE_SYMBOL and NOKPROBE_SYMBOL just adds the symbol to |
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* a blacklist. The former is for core kprobe functions/data, the |
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* latter is for those that incdentially must be excluded from probing |
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* and allows them to be linked at more optimal location within text. |
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*/ |
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#ifdef CONFIG_KPROBES |
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#define _ASM_NOKPROBE_SYMBOL(entry) \ |
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.pushsection "_kprobe_blacklist","aw"; \ |
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PPC_LONG (entry) ; \ |
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.popsection |
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#else |
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#define _ASM_NOKPROBE_SYMBOL(entry) |
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#endif |
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#define FUNC_START(name) _GLOBAL(name) |
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#define FUNC_END(name) |
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/* |
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* LOAD_REG_IMMEDIATE(rn, expr) |
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* Loads the value of the constant expression 'expr' into register 'rn' |
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* using immediate instructions only. Use this when it's important not |
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* to reference other data (i.e. on ppc64 when the TOC pointer is not |
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* valid) and when 'expr' is a constant or absolute address. |
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* |
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* LOAD_REG_ADDR(rn, name) |
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* Loads the address of label 'name' into register 'rn'. Use this when |
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* you don't particularly need immediate instructions only, but you need |
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* the whole address in one register (e.g. it's a structure address and |
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* you want to access various offsets within it). On ppc32 this is |
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* identical to LOAD_REG_IMMEDIATE. |
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* |
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* LOAD_REG_ADDR_PIC(rn, name) |
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* Loads the address of label 'name' into register 'run'. Use this when |
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* the kernel doesn't run at the linked or relocated address. Please |
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* note that this macro will clobber the lr register. |
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* |
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* LOAD_REG_ADDRBASE(rn, name) |
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* ADDROFF(name) |
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* LOAD_REG_ADDRBASE loads part of the address of label 'name' into |
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* register 'rn'. ADDROFF(name) returns the remainder of the address as |
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* a constant expression. ADDROFF(name) is a signed expression < 16 bits |
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* in size, so is suitable for use directly as an offset in load and store |
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* instructions. Use this when loading/storing a single word or less as: |
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* LOAD_REG_ADDRBASE(rX, name) |
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* ld rY,ADDROFF(name)(rX) |
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*/ |
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/* Be careful, this will clobber the lr register. */ |
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#define LOAD_REG_ADDR_PIC(reg, name) \ |
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bl 0f; \ |
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0: mflr reg; \ |
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addis reg,reg,(name - 0b)@ha; \ |
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addi reg,reg,(name - 0b)@l; |
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#if defined(__powerpc64__) && defined(HAVE_AS_ATHIGH) |
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#define __AS_ATHIGH high |
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#else |
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#define __AS_ATHIGH h |
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#endif |
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.macro __LOAD_REG_IMMEDIATE_32 r, x |
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.if (\x) >= 0x8000 || (\x) < -0x8000 |
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lis \r, (\x)@__AS_ATHIGH |
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.if (\x) & 0xffff != 0 |
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ori \r, \r, (\x)@l |
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.endif |
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.else |
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li \r, (\x)@l |
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.endif |
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.endm |
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.macro __LOAD_REG_IMMEDIATE r, x |
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.if (\x) >= 0x80000000 || (\x) < -0x80000000 |
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__LOAD_REG_IMMEDIATE_32 \r, (\x) >> 32 |
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sldi \r, \r, 32 |
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.if (\x) & 0xffff0000 != 0 |
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oris \r, \r, (\x)@__AS_ATHIGH |
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.endif |
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.if (\x) & 0xffff != 0 |
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ori \r, \r, (\x)@l |
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.endif |
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.else |
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__LOAD_REG_IMMEDIATE_32 \r, \x |
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.endif |
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.endm |
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#ifdef __powerpc64__ |
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#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE reg, expr |
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#define LOAD_REG_IMMEDIATE_SYM(reg, tmp, expr) \ |
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lis tmp, (expr)@highest; \ |
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lis reg, (expr)@__AS_ATHIGH; \ |
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ori tmp, tmp, (expr)@higher; \ |
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ori reg, reg, (expr)@l; \ |
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rldimi reg, tmp, 32, 0 |
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#define LOAD_REG_ADDR(reg,name) \ |
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ld reg,name@got(r2) |
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#define LOAD_REG_ADDRBASE(reg,name) LOAD_REG_ADDR(reg,name) |
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#define ADDROFF(name) 0 |
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/* offsets for stack frame layout */ |
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#define LRSAVE 16 |
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#else /* 32-bit */ |
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#define LOAD_REG_IMMEDIATE(reg, expr) __LOAD_REG_IMMEDIATE_32 reg, expr |
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#define LOAD_REG_IMMEDIATE_SYM(reg,expr) \ |
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lis reg,(expr)@ha; \ |
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addi reg,reg,(expr)@l; |
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#define LOAD_REG_ADDR(reg,name) LOAD_REG_IMMEDIATE_SYM(reg, name) |
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#define LOAD_REG_ADDRBASE(reg, name) lis reg,name@ha |
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#define ADDROFF(name) name@l |
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/* offsets for stack frame layout */ |
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#define LRSAVE 4 |
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#endif |
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/* various errata or part fixups */ |
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#if defined(CONFIG_PPC_CELL) || defined(CONFIG_PPC_FSL_BOOK3E) |
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#define MFTB(dest) \ |
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90: mfspr dest, SPRN_TBRL; \ |
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BEGIN_FTR_SECTION_NESTED(96); \ |
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cmpwi dest,0; \ |
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beq- 90b; \ |
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END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) |
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#else |
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#define MFTB(dest) MFTBL(dest) |
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#endif |
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#ifdef CONFIG_PPC_8xx |
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#define MFTBL(dest) mftb dest |
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#define MFTBU(dest) mftbu dest |
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#else |
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#define MFTBL(dest) mfspr dest, SPRN_TBRL |
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#define MFTBU(dest) mfspr dest, SPRN_TBRU |
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#endif |
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#ifndef CONFIG_SMP |
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#define TLBSYNC |
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#else |
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#define TLBSYNC tlbsync; sync |
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#endif |
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#ifdef CONFIG_PPC64 |
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#define MTOCRF(FXM, RS) \ |
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BEGIN_FTR_SECTION_NESTED(848); \ |
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mtcrf (FXM), RS; \ |
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FTR_SECTION_ELSE_NESTED(848); \ |
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mtocrf (FXM), RS; \ |
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ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848) |
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#endif |
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/* |
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* This instruction is not implemented on the PPC 603 or 601; however, on |
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* the 403GCX and 405GP tlbia IS defined and tlbie is not. |
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* All of these instructions exist in the 8xx, they have magical powers, |
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* and they must be used. |
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*/ |
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#if !defined(CONFIG_4xx) && !defined(CONFIG_PPC_8xx) |
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#define tlbia \ |
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li r4,1024; \ |
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mtctr r4; \ |
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lis r4,KERNELBASE@h; \ |
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.machine push; \ |
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.machine "power4"; \ |
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0: tlbie r4; \ |
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.machine pop; \ |
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addi r4,r4,0x1000; \ |
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bdnz 0b |
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#endif |
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#ifdef CONFIG_IBM440EP_ERR42 |
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#define PPC440EP_ERR42 isync |
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#else |
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#define PPC440EP_ERR42 |
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#endif |
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/* The following stops all load and store data streams associated with stream |
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* ID (ie. streams created explicitly). The embedded and server mnemonics for |
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* dcbt are different so this must only be used for server. |
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*/ |
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#define DCBT_BOOK3S_STOP_ALL_STREAM_IDS(scratch) \ |
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lis scratch,0x60000000@h; \ |
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dcbt 0,scratch,0b01010 |
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/* |
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* toreal/fromreal/tophys/tovirt macros. 32-bit BookE makes them |
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* keep the address intact to be compatible with code shared with |
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* 32-bit classic. |
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* |
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* On the other hand, I find it useful to have them behave as expected |
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* by their name (ie always do the addition) on 64-bit BookE |
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*/ |
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#if defined(CONFIG_BOOKE) && !defined(CONFIG_PPC64) |
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#define toreal(rd) |
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#define fromreal(rd) |
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/* |
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* We use addis to ensure compatibility with the "classic" ppc versions of |
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* these macros, which use rs = 0 to get the tophys offset in rd, rather than |
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* converting the address in r0, and so this version has to do that too |
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* (i.e. set register rd to 0 when rs == 0). |
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*/ |
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#define tophys(rd,rs) \ |
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addis rd,rs,0 |
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#define tovirt(rd,rs) \ |
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addis rd,rs,0 |
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#elif defined(CONFIG_PPC64) |
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#define toreal(rd) /* we can access c000... in real mode */ |
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#define fromreal(rd) |
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#define tophys(rd,rs) \ |
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clrldi rd,rs,2 |
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#define tovirt(rd,rs) \ |
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rotldi rd,rs,16; \ |
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ori rd,rd,((KERNELBASE>>48)&0xFFFF);\ |
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rotldi rd,rd,48 |
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#else |
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#define toreal(rd) tophys(rd,rd) |
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#define fromreal(rd) tovirt(rd,rd) |
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#define tophys(rd, rs) addis rd, rs, -PAGE_OFFSET@h |
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#define tovirt(rd, rs) addis rd, rs, PAGE_OFFSET@h |
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#endif |
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#ifdef CONFIG_PPC_BOOK3S_64 |
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#define MTMSRD(r) mtmsrd r |
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#define MTMSR_EERI(reg) mtmsrd reg,1 |
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#else |
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#define MTMSRD(r) mtmsr r |
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#define MTMSR_EERI(reg) mtmsr reg |
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#endif |
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#endif /* __KERNEL__ */ |
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/* The boring bits... */ |
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/* Condition Register Bit Fields */ |
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#define cr0 0 |
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#define cr1 1 |
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#define cr2 2 |
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#define cr3 3 |
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#define cr4 4 |
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#define cr5 5 |
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#define cr6 6 |
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#define cr7 7 |
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/* |
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* General Purpose Registers (GPRs) |
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* |
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* The lower case r0-r31 should be used in preference to the upper |
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* case R0-R31 as they provide more error checking in the assembler. |
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* Use R0-31 only when really nessesary. |
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*/ |
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#define r0 %r0 |
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#define r1 %r1 |
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#define r2 %r2 |
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#define r3 %r3 |
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#define r4 %r4 |
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#define r5 %r5 |
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#define r6 %r6 |
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#define r7 %r7 |
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#define r8 %r8 |
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#define r9 %r9 |
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#define r10 %r10 |
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#define r11 %r11 |
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#define r12 %r12 |
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#define r13 %r13 |
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#define r14 %r14 |
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#define r15 %r15 |
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#define r16 %r16 |
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#define r17 %r17 |
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#define r18 %r18 |
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#define r19 %r19 |
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#define r20 %r20 |
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#define r21 %r21 |
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#define r22 %r22 |
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#define r23 %r23 |
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#define r24 %r24 |
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#define r25 %r25 |
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#define r26 %r26 |
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#define r27 %r27 |
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#define r28 %r28 |
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#define r29 %r29 |
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#define r30 %r30 |
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#define r31 %r31 |
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/* Floating Point Registers (FPRs) */ |
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#define fr0 0 |
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#define fr1 1 |
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#define fr2 2 |
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#define fr3 3 |
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#define fr4 4 |
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#define fr5 5 |
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#define fr6 6 |
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#define fr7 7 |
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#define fr8 8 |
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#define fr9 9 |
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#define fr10 10 |
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#define fr11 11 |
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#define fr12 12 |
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#define fr13 13 |
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#define fr14 14 |
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#define fr15 15 |
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#define fr16 16 |
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#define fr17 17 |
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#define fr18 18 |
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#define fr19 19 |
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#define fr20 20 |
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#define fr21 21 |
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#define fr22 22 |
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#define fr23 23 |
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#define fr24 24 |
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#define fr25 25 |
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#define fr26 26 |
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#define fr27 27 |
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#define fr28 28 |
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#define fr29 29 |
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#define fr30 30 |
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#define fr31 31 |
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/* AltiVec Registers (VPRs) */ |
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#define v0 0 |
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#define v1 1 |
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#define v2 2 |
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#define v3 3 |
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#define v4 4 |
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#define v5 5 |
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#define v6 6 |
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#define v7 7 |
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#define v8 8 |
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#define v9 9 |
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#define v10 10 |
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#define v11 11 |
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#define v12 12 |
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#define v13 13 |
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#define v14 14 |
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#define v15 15 |
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#define v16 16 |
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#define v17 17 |
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#define v18 18 |
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#define v19 19 |
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#define v20 20 |
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#define v21 21 |
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#define v22 22 |
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#define v23 23 |
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#define v24 24 |
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#define v25 25 |
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#define v26 26 |
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#define v27 27 |
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#define v28 28 |
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#define v29 29 |
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#define v30 30 |
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#define v31 31 |
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/* VSX Registers (VSRs) */ |
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#define vs0 0 |
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#define vs1 1 |
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#define vs2 2 |
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#define vs3 3 |
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#define vs4 4 |
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#define vs5 5 |
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#define vs6 6 |
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#define vs7 7 |
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#define vs8 8 |
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#define vs9 9 |
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#define vs10 10 |
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#define vs11 11 |
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#define vs12 12 |
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#define vs13 13 |
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#define vs14 14 |
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#define vs15 15 |
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#define vs16 16 |
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#define vs17 17 |
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#define vs18 18 |
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#define vs19 19 |
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#define vs20 20 |
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#define vs21 21 |
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#define vs22 22 |
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#define vs23 23 |
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#define vs24 24 |
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#define vs25 25 |
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#define vs26 26 |
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#define vs27 27 |
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#define vs28 28 |
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#define vs29 29 |
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#define vs30 30 |
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#define vs31 31 |
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#define vs32 32 |
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#define vs33 33 |
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#define vs34 34 |
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#define vs35 35 |
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#define vs36 36 |
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#define vs37 37 |
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#define vs38 38 |
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#define vs39 39 |
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#define vs40 40 |
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#define vs41 41 |
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#define vs42 42 |
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#define vs43 43 |
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#define vs44 44 |
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#define vs45 45 |
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#define vs46 46 |
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#define vs47 47 |
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#define vs48 48 |
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#define vs49 49 |
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#define vs50 50 |
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#define vs51 51 |
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#define vs52 52 |
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#define vs53 53 |
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#define vs54 54 |
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#define vs55 55 |
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#define vs56 56 |
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#define vs57 57 |
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#define vs58 58 |
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#define vs59 59 |
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#define vs60 60 |
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#define vs61 61 |
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#define vs62 62 |
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#define vs63 63 |
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/* SPE Registers (EVPRs) */ |
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#define evr0 0 |
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#define evr1 1 |
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#define evr2 2 |
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#define evr3 3 |
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#define evr4 4 |
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#define evr5 5 |
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#define evr6 6 |
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#define evr7 7 |
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#define evr8 8 |
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#define evr9 9 |
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#define evr10 10 |
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#define evr11 11 |
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#define evr12 12 |
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#define evr13 13 |
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#define evr14 14 |
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#define evr15 15 |
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#define evr16 16 |
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#define evr17 17 |
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#define evr18 18 |
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#define evr19 19 |
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#define evr20 20 |
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#define evr21 21 |
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#define evr22 22 |
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#define evr23 23 |
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#define evr24 24 |
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#define evr25 25 |
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#define evr26 26 |
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#define evr27 27 |
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#define evr28 28 |
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#define evr29 29 |
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#define evr30 30 |
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#define evr31 31 |
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/* some stab codes */ |
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#define N_FUN 36 |
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#define N_RSYM 64 |
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#define N_SLINE 68 |
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#define N_SO 100 |
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#define RFSCV .long 0x4c0000a4 |
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/* |
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* Create an endian fixup trampoline |
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* |
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* This starts with a "tdi 0,0,0x48" instruction which is |
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* essentially a "trap never", and thus akin to a nop. |
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* |
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* The opcode for this instruction read with the wrong endian |
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* however results in a b . + 8 |
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* |
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* So essentially we use that trick to execute the following |
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* trampoline in "reverse endian" if we are running with the |
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* MSR_LE bit set the "wrong" way for whatever endianness the |
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* kernel is built for. |
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*/ |
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#ifdef CONFIG_PPC_BOOK3E |
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#define FIXUP_ENDIAN |
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#else |
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/* |
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* This version may be used in HV or non-HV context. |
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* MSR[EE] must be disabled. |
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*/ |
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#define FIXUP_ENDIAN \ |
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tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ |
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b 191f; /* Skip trampoline if endian is good */ \ |
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.long 0xa600607d; /* mfmsr r11 */ \ |
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.long 0x01006b69; /* xori r11,r11,1 */ \ |
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.long 0x00004039; /* li r10,0 */ \ |
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.long 0x6401417d; /* mtmsrd r10,1 */ \ |
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.long 0x05009f42; /* bcl 20,31,$+4 */ \ |
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.long 0xa602487d; /* mflr r10 */ \ |
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.long 0x14004a39; /* addi r10,r10,20 */ \ |
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.long 0xa6035a7d; /* mtsrr0 r10 */ \ |
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.long 0xa6037b7d; /* mtsrr1 r11 */ \ |
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.long 0x2400004c; /* rfid */ \ |
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191: |
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/* |
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* This version that may only be used with MSR[HV]=1 |
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* - Does not clear MSR[RI], so more robust. |
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* - Slightly smaller and faster. |
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*/ |
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#define FIXUP_ENDIAN_HV \ |
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tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ |
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b 191f; /* Skip trampoline if endian is good */ \ |
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.long 0xa600607d; /* mfmsr r11 */ \ |
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.long 0x01006b69; /* xori r11,r11,1 */ \ |
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.long 0x05009f42; /* bcl 20,31,$+4 */ \ |
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.long 0xa602487d; /* mflr r10 */ \ |
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.long 0x14004a39; /* addi r10,r10,20 */ \ |
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.long 0xa64b5a7d; /* mthsrr0 r10 */ \ |
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.long 0xa64b7b7d; /* mthsrr1 r11 */ \ |
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.long 0x2402004c; /* hrfid */ \ |
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191: |
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#endif /* !CONFIG_PPC_BOOK3E */ |
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#endif /* __ASSEMBLY__ */ |
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/* |
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* Helper macro for exception table entries |
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*/ |
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#define EX_TABLE(_fault, _target) \ |
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stringify_in_c(.section __ex_table,"a";)\ |
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stringify_in_c(.balign 4;) \ |
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stringify_in_c(.long (_fault) - . ;) \ |
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stringify_in_c(.long (_target) - . ;) \ |
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stringify_in_c(.previous) |
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#define SOFT_MASK_TABLE(_start, _end) \ |
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stringify_in_c(.section __soft_mask_table,"a";)\ |
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stringify_in_c(.balign 8;) \ |
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stringify_in_c(.llong (_start);) \ |
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stringify_in_c(.llong (_end);) \ |
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stringify_in_c(.previous) |
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#define RESTART_TABLE(_start, _end, _target) \ |
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stringify_in_c(.section __restart_table,"a";)\ |
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stringify_in_c(.balign 8;) \ |
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stringify_in_c(.llong (_start);) \ |
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stringify_in_c(.llong (_end);) \ |
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stringify_in_c(.llong (_target);) \ |
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stringify_in_c(.previous) |
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#ifdef CONFIG_PPC_FSL_BOOK3E |
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#define BTB_FLUSH(reg) \ |
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lis reg,BUCSR_INIT@h; \ |
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ori reg,reg,BUCSR_INIT@l; \ |
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mtspr SPRN_BUCSR,reg; \ |
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isync; |
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#else |
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#define BTB_FLUSH(reg) |
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#endif /* CONFIG_PPC_FSL_BOOK3E */ |
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#endif /* _ASM_POWERPC_PPC_ASM_H */
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