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128 lines
4.9 KiB
128 lines
4.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_POWERPC_NOHASH_32_PTE_44x_H |
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#define _ASM_POWERPC_NOHASH_32_PTE_44x_H |
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#ifdef __KERNEL__ |
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/* |
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* Definitions for PPC440 |
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* |
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* Because of the 3 word TLB entries to support 36-bit addressing, |
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* the attribute are difficult to map in such a fashion that they |
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* are easily loaded during exception processing. I decided to |
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* organize the entry so the ERPN is the only portion in the |
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* upper word of the PTE and the attribute bits below are packed |
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* in as sensibly as they can be in the area below a 4KB page size |
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* oriented RPN. This at least makes it easy to load the RPN and |
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* ERPN fields in the TLB. -Matt |
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* |
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* This isn't entirely true anymore, at least some bits are now |
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* easier to move into the TLB from the PTE. -BenH. |
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* |
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* Note that these bits preclude future use of a page size |
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* less than 4KB. |
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* |
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* |
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* PPC 440 core has following TLB attribute fields; |
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* |
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* TLB1: |
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* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
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* RPN................................. - - - - - - ERPN....... |
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* |
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* TLB2: |
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* 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 |
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* - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR |
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* |
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* Newer 440 cores (440x6 as used on AMCC 460EX/460GT) have additional |
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* TLB2 storage attribute fields. Those are: |
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* |
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* TLB2: |
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* 0...10 11 12 13 14 15 16...31 |
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* no change WL1 IL1I IL1D IL2I IL2D no change |
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* |
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* There are some constrains and options, to decide mapping software bits |
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* into TLB entry. |
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* |
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* - PRESENT *must* be in the bottom three bits because swap cache |
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* entries use the top 29 bits for TLB2. |
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* |
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* - CACHE COHERENT bit (M) has no effect on original PPC440 cores, |
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* because it doesn't support SMP. However, some later 460 variants |
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* have -some- form of SMP support and so I keep the bit there for |
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* future use |
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* |
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* With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used |
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* for memory protection related functions (see PTE structure in |
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* include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the |
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* above bits. Note that the bit values are CPU specific, not architecture |
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* specific. |
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* |
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* The kernel PTE entry holds an arch-dependent swp_entry structure under |
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* certain situations. In other words, in such situations some portion of |
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* the PTE bits are used as a swp_entry. In the PPC implementation, the |
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* 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still |
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* hold protection values. That means the three protection bits are |
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* reserved for both PTE and SWAP entry at the most significant three |
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* LSBs. |
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* |
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* There are three protection bits available for SWAP entry: |
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* _PAGE_PRESENT |
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* _PAGE_HASHPTE (if HW has) |
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* |
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* So those three bits have to be inside of 0-2nd LSB of PTE. |
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* |
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*/ |
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#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ |
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#define _PAGE_RW 0x00000002 /* S: Write permission */ |
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#define _PAGE_EXEC 0x00000004 /* H: Execute permission */ |
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#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ |
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#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */ |
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#define _PAGE_SPECIAL 0x00000020 /* S: Special page */ |
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#define _PAGE_USER 0x00000040 /* S: User page */ |
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#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ |
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#define _PAGE_GUARDED 0x00000100 /* H: G bit */ |
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#define _PAGE_COHERENT 0x00000200 /* H: M bit */ |
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#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ |
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#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ |
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/* No page size encoding in the linux PTE */ |
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#define _PAGE_PSIZE 0 |
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#define _PAGE_KERNEL_RO 0 |
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#define _PAGE_KERNEL_ROX _PAGE_EXEC |
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW) |
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC) |
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/* TODO: Add large page lowmem mapping support */ |
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#define _PMD_PRESENT 0 |
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#define _PMD_PRESENT_MASK (PAGE_MASK) |
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#define _PMD_BAD (~PAGE_MASK) |
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#define _PMD_USER 0 |
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/* ERPN in a PTE never gets cleared, ignore it */ |
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#define _PTE_NONE_MASK 0xffffffff00000000ULL |
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/* |
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* We define 2 sets of base prot bits, one for basic pages (ie, |
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* cacheable kernel and user pages) and one for non cacheable |
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* pages. We always set _PAGE_COHERENT when SMP is enabled or |
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* the processor might need it for DMA coherency. |
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*/ |
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#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) |
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#if defined(CONFIG_SMP) |
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#define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT) |
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#else |
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#define _PAGE_BASE (_PAGE_BASE_NC) |
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#endif |
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/* Permission masks used to generate the __P and __S table */ |
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#define PAGE_NONE __pgprot(_PAGE_BASE) |
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#define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW) |
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#define PAGE_SHARED_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC) |
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#define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER) |
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#define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
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#define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER) |
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#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC) |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */
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