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99 lines
2.9 KiB
99 lines
2.9 KiB
/* |
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* include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions |
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* |
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* Copyright (C) 1997 Geert Uytterhoeven |
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* |
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* This file is based on the following documentation: |
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* |
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* Macintosh Technology in the Common Hardware Reference Platform |
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* Apple Computer, Inc. |
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* |
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* © Copyright 1995 Apple Computer, Inc. All rights reserved. |
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* |
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* It's available online from https://www.cpu.lu/~mlan/ftp/MacTech.pdf |
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* You can obtain paper copies of this book from computer bookstores or by |
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* writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San |
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* Francisco, CA 94104. Reference ISBN 1-55860-393-X. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive |
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* for more details. |
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*/ |
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#ifndef _ASMPPC_HYDRA_H |
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#define _ASMPPC_HYDRA_H |
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#ifdef __KERNEL__ |
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struct Hydra { |
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/* DBDMA Controller Register Space */ |
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char Pad1[0x30]; |
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u_int CachePD; |
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u_int IDs; |
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u_int Feature_Control; |
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char Pad2[0x7fc4]; |
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/* DBDMA Channel Register Space */ |
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char SCSI_DMA[0x100]; |
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char Pad3[0x300]; |
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char SCCA_Tx_DMA[0x100]; |
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char SCCA_Rx_DMA[0x100]; |
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char SCCB_Tx_DMA[0x100]; |
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char SCCB_Rx_DMA[0x100]; |
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char Pad4[0x7800]; |
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/* Device Register Space */ |
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char SCSI[0x1000]; |
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char ADB[0x1000]; |
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char SCC_Legacy[0x1000]; |
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char SCC[0x1000]; |
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char Pad9[0x2000]; |
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char VIA[0x2000]; |
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char Pad10[0x28000]; |
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char OpenPIC[0x40000]; |
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}; |
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extern volatile struct Hydra __iomem *Hydra; |
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/* |
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* Feature Control Register |
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*/ |
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#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */ |
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#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */ |
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#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */ |
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#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */ |
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#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */ |
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#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */ |
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#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */ |
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#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */ |
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#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */ |
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/* |
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* OpenPIC Interrupt Sources |
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*/ |
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#define HYDRA_INT_SIO 0 |
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#define HYDRA_INT_SCSI_DMA 1 |
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#define HYDRA_INT_SCCA_TX_DMA 2 |
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#define HYDRA_INT_SCCA_RX_DMA 3 |
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#define HYDRA_INT_SCCB_TX_DMA 4 |
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#define HYDRA_INT_SCCB_RX_DMA 5 |
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#define HYDRA_INT_SCSI 6 |
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#define HYDRA_INT_SCCA 7 |
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#define HYDRA_INT_SCCB 8 |
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#define HYDRA_INT_VIA 9 |
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#define HYDRA_INT_ADB 10 |
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#define HYDRA_INT_ADB_NMI 11 |
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#define HYDRA_INT_EXT1 12 /* PCI IRQW */ |
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#define HYDRA_INT_EXT2 13 /* PCI IRQX */ |
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#define HYDRA_INT_EXT3 14 /* PCI IRQY */ |
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#define HYDRA_INT_EXT4 15 /* PCI IRQZ */ |
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#define HYDRA_INT_EXT5 16 /* IDE Primary/Secondary */ |
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#define HYDRA_INT_EXT6 17 /* IDE Secondary */ |
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#define HYDRA_INT_EXT7 18 /* Power Off Request */ |
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#define HYDRA_INT_SPARE 19 |
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#endif /* __KERNEL__ */ |
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#endif /* _ASMPPC_HYDRA_H */
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