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420 lines
10 KiB
420 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 1999 Cort Dougan <[email protected]> |
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*/ |
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#ifndef _ASM_POWERPC_HW_IRQ_H |
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#define _ASM_POWERPC_HW_IRQ_H |
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#ifdef __KERNEL__ |
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#include <linux/errno.h> |
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#include <linux/compiler.h> |
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#include <asm/ptrace.h> |
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#include <asm/processor.h> |
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#ifdef CONFIG_PPC64 |
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/* |
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* PACA flags in paca->irq_happened. |
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* |
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* This bits are set when interrupts occur while soft-disabled |
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* and allow a proper replay. |
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* |
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* The PACA_IRQ_HARD_DIS is set whenever we hard disable. It is almost |
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* always in synch with the MSR[EE] state, except: |
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* - A window in interrupt entry, where hardware disables MSR[EE] and that |
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* must be "reconciled" with the soft mask state. |
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* - NMI interrupts that hit in awkward places, until they fix the state. |
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* - When local irqs are being enabled and state is being fixed up. |
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* - When returning from an interrupt there are some windows where this |
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* can become out of synch, but gets fixed before the RFI or before |
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* executing the next user instruction (see arch/powerpc/kernel/interrupt.c). |
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*/ |
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#define PACA_IRQ_HARD_DIS 0x01 |
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#define PACA_IRQ_DBELL 0x02 |
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#define PACA_IRQ_EE 0x04 |
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#define PACA_IRQ_DEC 0x08 /* Or FIT */ |
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#define PACA_IRQ_HMI 0x10 |
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#define PACA_IRQ_PMI 0x20 |
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/* |
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* Some soft-masked interrupts must be hard masked until they are replayed |
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* (e.g., because the soft-masked handler does not clear the exception). |
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*/ |
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#ifdef CONFIG_PPC_BOOK3S |
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#define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE|PACA_IRQ_PMI) |
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#else |
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#define PACA_IRQ_MUST_HARD_MASK (PACA_IRQ_EE) |
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#endif |
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#endif /* CONFIG_PPC64 */ |
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/* |
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* flags for paca->irq_soft_mask |
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*/ |
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#define IRQS_ENABLED 0 |
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#define IRQS_DISABLED 1 /* local_irq_disable() interrupts */ |
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#define IRQS_PMI_DISABLED 2 |
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#define IRQS_ALL_DISABLED (IRQS_DISABLED | IRQS_PMI_DISABLED) |
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#ifndef __ASSEMBLY__ |
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static inline void __hard_irq_enable(void) |
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{ |
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if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) |
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wrtee(MSR_EE); |
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else if (IS_ENABLED(CONFIG_PPC_8xx)) |
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wrtspr(SPRN_EIE); |
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else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
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__mtmsrd(MSR_EE | MSR_RI, 1); |
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else |
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mtmsr(mfmsr() | MSR_EE); |
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} |
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static inline void __hard_irq_disable(void) |
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{ |
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if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) |
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wrtee(0); |
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else if (IS_ENABLED(CONFIG_PPC_8xx)) |
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wrtspr(SPRN_EID); |
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else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
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__mtmsrd(MSR_RI, 1); |
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else |
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mtmsr(mfmsr() & ~MSR_EE); |
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} |
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static inline void __hard_EE_RI_disable(void) |
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{ |
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if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) |
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wrtee(0); |
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else if (IS_ENABLED(CONFIG_PPC_8xx)) |
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wrtspr(SPRN_NRI); |
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else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
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__mtmsrd(0, 1); |
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else |
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mtmsr(mfmsr() & ~(MSR_EE | MSR_RI)); |
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} |
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static inline void __hard_RI_enable(void) |
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{ |
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if (IS_ENABLED(CONFIG_BOOKE) || IS_ENABLED(CONFIG_40x)) |
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return; |
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if (IS_ENABLED(CONFIG_PPC_8xx)) |
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wrtspr(SPRN_EID); |
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else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) |
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__mtmsrd(MSR_RI, 1); |
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else |
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mtmsr(mfmsr() | MSR_RI); |
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} |
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#ifdef CONFIG_PPC64 |
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#include <asm/paca.h> |
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static inline notrace unsigned long irq_soft_mask_return(void) |
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{ |
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unsigned long flags; |
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asm volatile( |
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"lbz %0,%1(13)" |
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: "=r" (flags) |
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: "i" (offsetof(struct paca_struct, irq_soft_mask))); |
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return flags; |
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} |
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/* |
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* The "memory" clobber acts as both a compiler barrier |
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* for the critical section and as a clobber because |
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* we changed paca->irq_soft_mask |
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*/ |
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static inline notrace void irq_soft_mask_set(unsigned long mask) |
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{ |
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#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG |
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/* |
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* The irq mask must always include the STD bit if any are set. |
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* |
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* and interrupts don't get replayed until the standard |
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* interrupt (local_irq_disable()) is unmasked. |
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* |
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* Other masks must only provide additional masking beyond |
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* the standard, and they are also not replayed until the |
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* standard interrupt becomes unmasked. |
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* |
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* This could be changed, but it will require partial |
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* unmasks to be replayed, among other things. For now, take |
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* the simple approach. |
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*/ |
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WARN_ON(mask && !(mask & IRQS_DISABLED)); |
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#endif |
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asm volatile( |
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"stb %0,%1(13)" |
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: |
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: "r" (mask), |
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"i" (offsetof(struct paca_struct, irq_soft_mask)) |
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: "memory"); |
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} |
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static inline notrace unsigned long irq_soft_mask_set_return(unsigned long mask) |
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{ |
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unsigned long flags; |
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#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG |
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WARN_ON(mask && !(mask & IRQS_DISABLED)); |
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#endif |
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asm volatile( |
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"lbz %0,%1(13); stb %2,%1(13)" |
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: "=&r" (flags) |
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: "i" (offsetof(struct paca_struct, irq_soft_mask)), |
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"r" (mask) |
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: "memory"); |
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return flags; |
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} |
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static inline notrace unsigned long irq_soft_mask_or_return(unsigned long mask) |
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{ |
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unsigned long flags, tmp; |
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asm volatile( |
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"lbz %0,%2(13); or %1,%0,%3; stb %1,%2(13)" |
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: "=&r" (flags), "=r" (tmp) |
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: "i" (offsetof(struct paca_struct, irq_soft_mask)), |
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"r" (mask) |
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: "memory"); |
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#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG |
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WARN_ON((mask | flags) && !((mask | flags) & IRQS_DISABLED)); |
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#endif |
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return flags; |
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} |
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static inline unsigned long arch_local_save_flags(void) |
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{ |
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return irq_soft_mask_return(); |
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} |
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static inline void arch_local_irq_disable(void) |
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{ |
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irq_soft_mask_set(IRQS_DISABLED); |
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} |
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extern void arch_local_irq_restore(unsigned long); |
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static inline void arch_local_irq_enable(void) |
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{ |
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arch_local_irq_restore(IRQS_ENABLED); |
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} |
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static inline unsigned long arch_local_irq_save(void) |
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{ |
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return irq_soft_mask_set_return(IRQS_DISABLED); |
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} |
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static inline bool arch_irqs_disabled_flags(unsigned long flags) |
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{ |
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return flags & IRQS_DISABLED; |
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} |
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static inline bool arch_irqs_disabled(void) |
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{ |
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return arch_irqs_disabled_flags(arch_local_save_flags()); |
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} |
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#ifdef CONFIG_PPC_BOOK3S |
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/* |
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* To support disabling and enabling of irq with PMI, set of |
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* new powerpc_local_irq_pmu_save() and powerpc_local_irq_restore() |
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* functions are added. These macros are implemented using generic |
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* linux local_irq_* code from include/linux/irqflags.h. |
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*/ |
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#define raw_local_irq_pmu_save(flags) \ |
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do { \ |
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typecheck(unsigned long, flags); \ |
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flags = irq_soft_mask_or_return(IRQS_DISABLED | \ |
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IRQS_PMI_DISABLED); \ |
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} while(0) |
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#define raw_local_irq_pmu_restore(flags) \ |
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do { \ |
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typecheck(unsigned long, flags); \ |
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arch_local_irq_restore(flags); \ |
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} while(0) |
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#ifdef CONFIG_TRACE_IRQFLAGS |
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#define powerpc_local_irq_pmu_save(flags) \ |
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do { \ |
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raw_local_irq_pmu_save(flags); \ |
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if (!raw_irqs_disabled_flags(flags)) \ |
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trace_hardirqs_off(); \ |
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} while(0) |
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#define powerpc_local_irq_pmu_restore(flags) \ |
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do { \ |
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if (!raw_irqs_disabled_flags(flags)) \ |
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trace_hardirqs_on(); \ |
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raw_local_irq_pmu_restore(flags); \ |
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} while(0) |
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#else |
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#define powerpc_local_irq_pmu_save(flags) \ |
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do { \ |
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raw_local_irq_pmu_save(flags); \ |
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} while(0) |
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#define powerpc_local_irq_pmu_restore(flags) \ |
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do { \ |
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raw_local_irq_pmu_restore(flags); \ |
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} while (0) |
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#endif /* CONFIG_TRACE_IRQFLAGS */ |
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#endif /* CONFIG_PPC_BOOK3S */ |
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#define hard_irq_disable() do { \ |
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unsigned long flags; \ |
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__hard_irq_disable(); \ |
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flags = irq_soft_mask_set_return(IRQS_ALL_DISABLED); \ |
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS; \ |
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if (!arch_irqs_disabled_flags(flags)) { \ |
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asm ("stdx %%r1, 0, %1 ;" \ |
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: "=m" (local_paca->saved_r1) \ |
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: "b" (&local_paca->saved_r1)); \ |
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trace_hardirqs_off(); \ |
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} \ |
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} while(0) |
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static inline bool __lazy_irq_pending(u8 irq_happened) |
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{ |
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return !!(irq_happened & ~PACA_IRQ_HARD_DIS); |
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} |
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/* |
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* Check if a lazy IRQ is pending. Should be called with IRQs hard disabled. |
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*/ |
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static inline bool lazy_irq_pending(void) |
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{ |
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return __lazy_irq_pending(get_paca()->irq_happened); |
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} |
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/* |
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* Check if a lazy IRQ is pending, with no debugging checks. |
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* Should be called with IRQs hard disabled. |
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* For use in RI disabled code or other constrained situations. |
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*/ |
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static inline bool lazy_irq_pending_nocheck(void) |
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{ |
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return __lazy_irq_pending(local_paca->irq_happened); |
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} |
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/* |
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* This is called by asynchronous interrupts to conditionally |
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* re-enable hard interrupts after having cleared the source |
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* of the interrupt. They are kept disabled if there is a different |
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* soft-masked interrupt pending that requires hard masking. |
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*/ |
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static inline void may_hard_irq_enable(void) |
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{ |
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if (!(get_paca()->irq_happened & PACA_IRQ_MUST_HARD_MASK)) { |
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get_paca()->irq_happened &= ~PACA_IRQ_HARD_DIS; |
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__hard_irq_enable(); |
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} |
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} |
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static inline bool arch_irq_disabled_regs(struct pt_regs *regs) |
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{ |
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return (regs->softe & IRQS_DISABLED); |
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} |
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extern bool prep_irq_for_idle(void); |
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extern bool prep_irq_for_idle_irqsoff(void); |
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extern void irq_set_pending_from_srr1(unsigned long srr1); |
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#define fini_irq_for_idle_irqsoff() trace_hardirqs_off(); |
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extern void force_external_irq_replay(void); |
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static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned long val) |
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{ |
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regs->softe = val; |
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} |
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#else /* CONFIG_PPC64 */ |
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static inline notrace unsigned long irq_soft_mask_return(void) |
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{ |
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return 0; |
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} |
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static inline unsigned long arch_local_save_flags(void) |
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{ |
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return mfmsr(); |
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} |
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static inline void arch_local_irq_restore(unsigned long flags) |
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{ |
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if (IS_ENABLED(CONFIG_BOOKE)) |
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wrtee(flags); |
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else |
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mtmsr(flags); |
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} |
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static inline unsigned long arch_local_irq_save(void) |
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{ |
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unsigned long flags = arch_local_save_flags(); |
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if (IS_ENABLED(CONFIG_BOOKE)) |
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wrtee(0); |
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else if (IS_ENABLED(CONFIG_PPC_8xx)) |
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wrtspr(SPRN_EID); |
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else |
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mtmsr(flags & ~MSR_EE); |
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return flags; |
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} |
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static inline void arch_local_irq_disable(void) |
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{ |
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__hard_irq_disable(); |
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} |
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static inline void arch_local_irq_enable(void) |
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{ |
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__hard_irq_enable(); |
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} |
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static inline bool arch_irqs_disabled_flags(unsigned long flags) |
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{ |
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return (flags & MSR_EE) == 0; |
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} |
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static inline bool arch_irqs_disabled(void) |
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{ |
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return arch_irqs_disabled_flags(arch_local_save_flags()); |
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} |
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#define hard_irq_disable() arch_local_irq_disable() |
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static inline bool arch_irq_disabled_regs(struct pt_regs *regs) |
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{ |
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return !(regs->msr & MSR_EE); |
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} |
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static inline bool may_hard_irq_enable(void) |
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{ |
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return false; |
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} |
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static inline void do_hard_irq_enable(void) |
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{ |
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BUILD_BUG(); |
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} |
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static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned long val) |
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{ |
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} |
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#endif /* CONFIG_PPC64 */ |
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#define ARCH_IRQ_INIT_FLAGS IRQ_NOREQUEST |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_POWERPC_HW_IRQ_H */
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