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612 lines
21 KiB
612 lines
21 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* MPC8xx Communication Processor Module. |
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* Copyright (c) 1997 Dan Malek ([email protected]) |
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* |
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* This file contains structures and information for the communication |
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* processor channels. Some CPM control and status is available |
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* through the MPC8xx internal memory map. See immap.h for details. |
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* This file only contains what I need for the moment, not the total |
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* CPM capabilities. I (or someone else) will add definitions as they |
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* are needed. -- Dan |
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* |
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* On the MBX board, EPPC-Bug loads CPM microcode into the first 512 |
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* bytes of the DP RAM and relocates the I2C parameter area to the |
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* IDMA1 space. The remaining DP RAM is available for buffer descriptors |
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* or other use. |
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*/ |
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#ifndef __CPM1__ |
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#define __CPM1__ |
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#include <linux/init.h> |
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#include <asm/8xx_immap.h> |
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#include <asm/ptrace.h> |
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#include <asm/cpm.h> |
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/* CPM Command register. |
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*/ |
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#define CPM_CR_RST ((ushort)0x8000) |
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#define CPM_CR_OPCODE ((ushort)0x0f00) |
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#define CPM_CR_CHAN ((ushort)0x00f0) |
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#define CPM_CR_FLG ((ushort)0x0001) |
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/* Channel numbers. |
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*/ |
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#define CPM_CR_CH_SCC1 ((ushort)0x0000) |
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#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ |
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#define CPM_CR_CH_SCC2 ((ushort)0x0004) |
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#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */ |
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#define CPM_CR_CH_TIMER CPM_CR_CH_SPI |
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#define CPM_CR_CH_SCC3 ((ushort)0x0008) |
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#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ |
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#define CPM_CR_CH_SCC4 ((ushort)0x000c) |
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#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ |
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#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) |
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/* Export the base address of the communication processor registers |
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* and dual port ram. |
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*/ |
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extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */ |
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#define cpm_dpalloc cpm_muram_alloc |
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#define cpm_dpfree cpm_muram_free |
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#define cpm_dpram_addr cpm_muram_addr |
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#define cpm_dpram_phys cpm_muram_dma |
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extern void cpm_setbrg(uint brg, uint rate); |
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extern void __init cpm_load_patch(cpm8xx_t *cp); |
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extern void cpm_reset(void); |
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/* Parameter RAM offsets. |
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*/ |
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#define PROFF_SCC1 ((uint)0x0000) |
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#define PROFF_IIC ((uint)0x0080) |
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#define PROFF_SCC2 ((uint)0x0100) |
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#define PROFF_SPI ((uint)0x0180) |
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#define PROFF_SCC3 ((uint)0x0200) |
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#define PROFF_SMC1 ((uint)0x0280) |
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#define PROFF_DSP1 ((uint)0x02c0) |
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#define PROFF_SCC4 ((uint)0x0300) |
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#define PROFF_SMC2 ((uint)0x0380) |
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/* Define enough so I can at least use the serial port as a UART. |
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* The MBX uses SMC1 as the host serial port. |
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*/ |
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typedef struct smc_uart { |
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ushort smc_rbase; /* Rx Buffer descriptor base address */ |
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ushort smc_tbase; /* Tx Buffer descriptor base address */ |
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u_char smc_rfcr; /* Rx function code */ |
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u_char smc_tfcr; /* Tx function code */ |
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ushort smc_mrblr; /* Max receive buffer length */ |
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uint smc_rstate; /* Internal */ |
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uint smc_idp; /* Internal */ |
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ushort smc_rbptr; /* Internal */ |
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ushort smc_ibc; /* Internal */ |
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uint smc_rxtmp; /* Internal */ |
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uint smc_tstate; /* Internal */ |
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uint smc_tdp; /* Internal */ |
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ushort smc_tbptr; /* Internal */ |
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ushort smc_tbc; /* Internal */ |
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uint smc_txtmp; /* Internal */ |
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ushort smc_maxidl; /* Maximum idle characters */ |
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ushort smc_tmpidl; /* Temporary idle counter */ |
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ushort smc_brklen; /* Last received break length */ |
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ushort smc_brkec; /* rcv'd break condition counter */ |
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ushort smc_brkcr; /* xmt break count register */ |
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ushort smc_rmask; /* Temporary bit mask */ |
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char res1[8]; /* Reserved */ |
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ushort smc_rpbase; /* Relocation pointer */ |
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} smc_uart_t; |
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/* Function code bits. |
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*/ |
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#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ |
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/* SMC uart mode register. |
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*/ |
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#define SMCMR_REN ((ushort)0x0001) |
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#define SMCMR_TEN ((ushort)0x0002) |
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#define SMCMR_DM ((ushort)0x000c) |
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#define SMCMR_SM_GCI ((ushort)0x0000) |
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#define SMCMR_SM_UART ((ushort)0x0020) |
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#define SMCMR_SM_TRANS ((ushort)0x0030) |
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#define SMCMR_SM_MASK ((ushort)0x0030) |
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#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ |
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#define SMCMR_REVD SMCMR_PM_EVEN |
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#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ |
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#define SMCMR_BS SMCMR_PEN |
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#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ |
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#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ |
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#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) |
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/* SMC2 as Centronics parallel printer. It is half duplex, in that |
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* it can only receive or transmit. The parameter ram values for |
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* each direction are either unique or properly overlap, so we can |
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* include them in one structure. |
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*/ |
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typedef struct smc_centronics { |
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ushort scent_rbase; |
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ushort scent_tbase; |
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u_char scent_cfcr; |
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u_char scent_smask; |
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ushort scent_mrblr; |
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uint scent_rstate; |
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uint scent_r_ptr; |
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ushort scent_rbptr; |
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ushort scent_r_cnt; |
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uint scent_rtemp; |
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uint scent_tstate; |
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uint scent_t_ptr; |
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ushort scent_tbptr; |
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ushort scent_t_cnt; |
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uint scent_ttemp; |
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ushort scent_max_sl; |
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ushort scent_sl_cnt; |
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ushort scent_character1; |
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ushort scent_character2; |
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ushort scent_character3; |
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ushort scent_character4; |
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ushort scent_character5; |
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ushort scent_character6; |
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ushort scent_character7; |
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ushort scent_character8; |
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ushort scent_rccm; |
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ushort scent_rccr; |
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} smc_cent_t; |
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/* Centronics Status Mask Register. |
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*/ |
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#define SMC_CENT_F ((u_char)0x08) |
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#define SMC_CENT_PE ((u_char)0x04) |
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#define SMC_CENT_S ((u_char)0x02) |
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/* SMC Event and Mask register. |
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*/ |
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#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ |
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#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ |
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#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ |
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#define SMCM_BSY ((unsigned char)0x04) |
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#define SMCM_TX ((unsigned char)0x02) |
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#define SMCM_RX ((unsigned char)0x01) |
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/* Baud rate generators. |
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*/ |
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#define CPM_BRG_RST ((uint)0x00020000) |
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#define CPM_BRG_EN ((uint)0x00010000) |
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#define CPM_BRG_EXTC_INT ((uint)0x00000000) |
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#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) |
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#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) |
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#define CPM_BRG_ATB ((uint)0x00002000) |
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#define CPM_BRG_CD_MASK ((uint)0x00001ffe) |
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#define CPM_BRG_DIV16 ((uint)0x00000001) |
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/* SI Clock Route Register |
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*/ |
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#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) |
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#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) |
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#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) |
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#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) |
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#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) |
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#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) |
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#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) |
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#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) |
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/* SCCs. |
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*/ |
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#define SCC_GSMRH_IRP ((uint)0x00040000) |
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#define SCC_GSMRH_GDE ((uint)0x00010000) |
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#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) |
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#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) |
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#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) |
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#define SCC_GSMRH_REVD ((uint)0x00002000) |
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#define SCC_GSMRH_TRX ((uint)0x00001000) |
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#define SCC_GSMRH_TTX ((uint)0x00000800) |
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#define SCC_GSMRH_CDP ((uint)0x00000400) |
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#define SCC_GSMRH_CTSP ((uint)0x00000200) |
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#define SCC_GSMRH_CDS ((uint)0x00000100) |
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#define SCC_GSMRH_CTSS ((uint)0x00000080) |
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#define SCC_GSMRH_TFL ((uint)0x00000040) |
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#define SCC_GSMRH_RFW ((uint)0x00000020) |
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#define SCC_GSMRH_TXSY ((uint)0x00000010) |
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#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) |
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#define SCC_GSMRH_SYNL8 ((uint)0x00000008) |
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#define SCC_GSMRH_SYNL4 ((uint)0x00000004) |
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#define SCC_GSMRH_RTSM ((uint)0x00000002) |
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#define SCC_GSMRH_RSYN ((uint)0x00000001) |
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#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ |
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#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) |
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#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) |
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#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) |
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#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) |
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#define SCC_GSMRL_TCI ((uint)0x10000000) |
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#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) |
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#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) |
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#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) |
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#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) |
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#define SCC_GSMRL_RINV ((uint)0x02000000) |
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#define SCC_GSMRL_TINV ((uint)0x01000000) |
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#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) |
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#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) |
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#define SCC_GSMRL_TPL_48 ((uint)0x00800000) |
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#define SCC_GSMRL_TPL_32 ((uint)0x00600000) |
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#define SCC_GSMRL_TPL_16 ((uint)0x00400000) |
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#define SCC_GSMRL_TPL_8 ((uint)0x00200000) |
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#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) |
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#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) |
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#define SCC_GSMRL_TPP_01 ((uint)0x00100000) |
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#define SCC_GSMRL_TPP_10 ((uint)0x00080000) |
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#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) |
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#define SCC_GSMRL_TEND ((uint)0x00040000) |
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#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) |
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#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) |
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#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) |
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#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) |
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#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) |
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#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) |
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#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) |
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#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) |
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#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) |
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#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) |
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#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) |
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#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) |
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#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) |
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#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) |
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#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) |
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#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) |
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#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) |
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#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) |
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#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ |
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#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) |
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#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) |
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#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) |
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#define SCC_GSMRL_ENR ((uint)0x00000020) |
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#define SCC_GSMRL_ENT ((uint)0x00000010) |
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#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) |
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#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a) |
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#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) |
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#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) |
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#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) |
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#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) |
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#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) |
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#define SCC_GSMRL_MODE_UART ((uint)0x00000004) |
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#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) |
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#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) |
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#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) |
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#define SCC_TODR_TOD ((ushort)0x8000) |
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/* SCC Event and Mask register. |
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*/ |
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#define SCCM_TXE ((unsigned char)0x10) |
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#define SCCM_BSY ((unsigned char)0x04) |
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#define SCCM_TX ((unsigned char)0x02) |
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#define SCCM_RX ((unsigned char)0x01) |
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typedef struct scc_param { |
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ushort scc_rbase; /* Rx Buffer descriptor base address */ |
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ushort scc_tbase; /* Tx Buffer descriptor base address */ |
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u_char scc_rfcr; /* Rx function code */ |
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u_char scc_tfcr; /* Tx function code */ |
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ushort scc_mrblr; /* Max receive buffer length */ |
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uint scc_rstate; /* Internal */ |
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uint scc_idp; /* Internal */ |
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ushort scc_rbptr; /* Internal */ |
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ushort scc_ibc; /* Internal */ |
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uint scc_rxtmp; /* Internal */ |
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uint scc_tstate; /* Internal */ |
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uint scc_tdp; /* Internal */ |
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ushort scc_tbptr; /* Internal */ |
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ushort scc_tbc; /* Internal */ |
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uint scc_txtmp; /* Internal */ |
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uint scc_rcrc; /* Internal */ |
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uint scc_tcrc; /* Internal */ |
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} sccp_t; |
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/* Function code bits. |
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*/ |
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#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ |
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/* CPM Ethernet through SCCx. |
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*/ |
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typedef struct scc_enet { |
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sccp_t sen_genscc; |
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uint sen_cpres; /* Preset CRC */ |
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uint sen_cmask; /* Constant mask for CRC */ |
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uint sen_crcec; /* CRC Error counter */ |
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uint sen_alec; /* alignment error counter */ |
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uint sen_disfc; /* discard frame counter */ |
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ushort sen_pads; /* Tx short frame pad character */ |
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ushort sen_retlim; /* Retry limit threshold */ |
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ushort sen_retcnt; /* Retry limit counter */ |
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ushort sen_maxflr; /* maximum frame length register */ |
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ushort sen_minflr; /* minimum frame length register */ |
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ushort sen_maxd1; /* maximum DMA1 length */ |
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ushort sen_maxd2; /* maximum DMA2 length */ |
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ushort sen_maxd; /* Rx max DMA */ |
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ushort sen_dmacnt; /* Rx DMA counter */ |
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ushort sen_maxb; /* Max BD byte count */ |
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ushort sen_gaddr1; /* Group address filter */ |
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ushort sen_gaddr2; |
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ushort sen_gaddr3; |
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ushort sen_gaddr4; |
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uint sen_tbuf0data0; /* Save area 0 - current frame */ |
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uint sen_tbuf0data1; /* Save area 1 - current frame */ |
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uint sen_tbuf0rba; /* Internal */ |
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uint sen_tbuf0crc; /* Internal */ |
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ushort sen_tbuf0bcnt; /* Internal */ |
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ushort sen_paddrh; /* physical address (MSB) */ |
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ushort sen_paddrm; |
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ushort sen_paddrl; /* physical address (LSB) */ |
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ushort sen_pper; /* persistence */ |
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ushort sen_rfbdptr; /* Rx first BD pointer */ |
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ushort sen_tfbdptr; /* Tx first BD pointer */ |
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ushort sen_tlbdptr; /* Tx last BD pointer */ |
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uint sen_tbuf1data0; /* Save area 0 - current frame */ |
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uint sen_tbuf1data1; /* Save area 1 - current frame */ |
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uint sen_tbuf1rba; /* Internal */ |
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uint sen_tbuf1crc; /* Internal */ |
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ushort sen_tbuf1bcnt; /* Internal */ |
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ushort sen_txlen; /* Tx Frame length counter */ |
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ushort sen_iaddr1; /* Individual address filter */ |
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ushort sen_iaddr2; |
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ushort sen_iaddr3; |
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ushort sen_iaddr4; |
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ushort sen_boffcnt; /* Backoff counter */ |
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/* NOTE: Some versions of the manual have the following items |
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* incorrectly documented. Below is the proper order. |
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*/ |
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ushort sen_taddrh; /* temp address (MSB) */ |
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ushort sen_taddrm; |
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ushort sen_taddrl; /* temp address (LSB) */ |
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} scc_enet_t; |
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/* SCC Event register as used by Ethernet. |
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*/ |
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#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ |
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#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ |
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#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ |
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#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ |
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#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ |
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#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ |
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/* SCC Mode Register (PMSR) as used by Ethernet. |
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*/ |
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#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ |
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#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ |
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#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ |
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#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ |
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#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ |
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#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ |
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#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ |
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#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ |
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#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ |
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#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ |
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#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ |
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#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ |
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#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ |
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/* SCC as UART |
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*/ |
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typedef struct scc_uart { |
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sccp_t scc_genscc; |
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char res1[8]; /* Reserved */ |
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ushort scc_maxidl; /* Maximum idle chars */ |
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ushort scc_idlc; /* temp idle counter */ |
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ushort scc_brkcr; /* Break count register */ |
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ushort scc_parec; /* receive parity error counter */ |
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ushort scc_frmec; /* receive framing error counter */ |
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ushort scc_nosec; /* receive noise counter */ |
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ushort scc_brkec; /* receive break condition counter */ |
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ushort scc_brkln; /* last received break length */ |
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ushort scc_uaddr1; /* UART address character 1 */ |
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ushort scc_uaddr2; /* UART address character 2 */ |
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ushort scc_rtemp; /* Temp storage */ |
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ushort scc_toseq; /* Transmit out of sequence char */ |
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ushort scc_char1; /* control character 1 */ |
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ushort scc_char2; /* control character 2 */ |
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ushort scc_char3; /* control character 3 */ |
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ushort scc_char4; /* control character 4 */ |
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ushort scc_char5; /* control character 5 */ |
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ushort scc_char6; /* control character 6 */ |
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ushort scc_char7; /* control character 7 */ |
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ushort scc_char8; /* control character 8 */ |
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ushort scc_rccm; /* receive control character mask */ |
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ushort scc_rccr; /* receive control character register */ |
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ushort scc_rlbc; /* receive last break character */ |
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} scc_uart_t; |
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|
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/* SCC Event and Mask registers when it is used as a UART. |
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*/ |
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#define UART_SCCM_GLR ((ushort)0x1000) |
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#define UART_SCCM_GLT ((ushort)0x0800) |
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#define UART_SCCM_AB ((ushort)0x0200) |
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#define UART_SCCM_IDL ((ushort)0x0100) |
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#define UART_SCCM_GRA ((ushort)0x0080) |
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#define UART_SCCM_BRKE ((ushort)0x0040) |
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#define UART_SCCM_BRKS ((ushort)0x0020) |
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#define UART_SCCM_CCR ((ushort)0x0008) |
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#define UART_SCCM_BSY ((ushort)0x0004) |
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#define UART_SCCM_TX ((ushort)0x0002) |
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#define UART_SCCM_RX ((ushort)0x0001) |
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|
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/* The SCC PMSR when used as a UART. |
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*/ |
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#define SCU_PSMR_FLC ((ushort)0x8000) |
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#define SCU_PSMR_SL ((ushort)0x4000) |
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#define SCU_PSMR_CL ((ushort)0x3000) |
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#define SCU_PSMR_UM ((ushort)0x0c00) |
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#define SCU_PSMR_FRZ ((ushort)0x0200) |
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#define SCU_PSMR_RZS ((ushort)0x0100) |
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#define SCU_PSMR_SYN ((ushort)0x0080) |
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#define SCU_PSMR_DRT ((ushort)0x0040) |
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#define SCU_PSMR_PEN ((ushort)0x0010) |
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#define SCU_PSMR_RPM ((ushort)0x000c) |
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#define SCU_PSMR_REVP ((ushort)0x0008) |
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#define SCU_PSMR_TPM ((ushort)0x0003) |
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#define SCU_PSMR_TEVP ((ushort)0x0002) |
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|
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/* CPM Transparent mode SCC. |
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*/ |
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typedef struct scc_trans { |
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sccp_t st_genscc; |
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uint st_cpres; /* Preset CRC */ |
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uint st_cmask; /* Constant mask for CRC */ |
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} scc_trans_t; |
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|
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/* IIC parameter RAM. |
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*/ |
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typedef struct iic { |
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ushort iic_rbase; /* Rx Buffer descriptor base address */ |
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ushort iic_tbase; /* Tx Buffer descriptor base address */ |
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u_char iic_rfcr; /* Rx function code */ |
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u_char iic_tfcr; /* Tx function code */ |
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ushort iic_mrblr; /* Max receive buffer length */ |
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uint iic_rstate; /* Internal */ |
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uint iic_rdp; /* Internal */ |
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ushort iic_rbptr; /* Internal */ |
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ushort iic_rbc; /* Internal */ |
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uint iic_rxtmp; /* Internal */ |
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uint iic_tstate; /* Internal */ |
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uint iic_tdp; /* Internal */ |
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ushort iic_tbptr; /* Internal */ |
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ushort iic_tbc; /* Internal */ |
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uint iic_txtmp; /* Internal */ |
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char res1[4]; /* Reserved */ |
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ushort iic_rpbase; /* Relocation pointer */ |
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char res2[2]; /* Reserved */ |
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} iic_t; |
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|
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/* |
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* RISC Controller Configuration Register definitons |
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*/ |
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#define RCCR_TIME 0x8000 /* RISC Timer Enable */ |
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#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */ |
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#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */ |
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|
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/* RISC Timer Parameter RAM offset */ |
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#define PROFF_RTMR ((uint)0x01B0) |
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|
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typedef struct risc_timer_pram { |
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unsigned short tm_base; /* RISC Timer Table Base Address */ |
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unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */ |
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unsigned short r_tmr; /* RISC Timer Mode Register */ |
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unsigned short r_tmv; /* RISC Timer Valid Register */ |
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unsigned long tm_cmd; /* RISC Timer Command Register */ |
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unsigned long tm_cnt; /* RISC Timer Internal Count */ |
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} rt_pram_t; |
|
|
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/* Bits in RISC Timer Command Register */ |
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#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */ |
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#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */ |
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#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */ |
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#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */ |
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#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */ |
|
|
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/* CPM interrupts. There are nearly 32 interrupts generated by CPM |
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* channels or devices. All of these are presented to the PPC core |
|
* as a single interrupt. The CPM interrupt handler dispatches its |
|
* own handlers, in a similar fashion to the PPC core handler. We |
|
* use the table as defined in the manuals (i.e. no special high |
|
* priority and SCC1 == SCCa, etc...). |
|
*/ |
|
#define CPMVEC_NR 32 |
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#define CPMVEC_PIO_PC15 ((ushort)0x1f) |
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#define CPMVEC_SCC1 ((ushort)0x1e) |
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#define CPMVEC_SCC2 ((ushort)0x1d) |
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#define CPMVEC_SCC3 ((ushort)0x1c) |
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#define CPMVEC_SCC4 ((ushort)0x1b) |
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#define CPMVEC_PIO_PC14 ((ushort)0x1a) |
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#define CPMVEC_TIMER1 ((ushort)0x19) |
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#define CPMVEC_PIO_PC13 ((ushort)0x18) |
|
#define CPMVEC_PIO_PC12 ((ushort)0x17) |
|
#define CPMVEC_SDMA_CB_ERR ((ushort)0x16) |
|
#define CPMVEC_IDMA1 ((ushort)0x15) |
|
#define CPMVEC_IDMA2 ((ushort)0x14) |
|
#define CPMVEC_TIMER2 ((ushort)0x12) |
|
#define CPMVEC_RISCTIMER ((ushort)0x11) |
|
#define CPMVEC_I2C ((ushort)0x10) |
|
#define CPMVEC_PIO_PC11 ((ushort)0x0f) |
|
#define CPMVEC_PIO_PC10 ((ushort)0x0e) |
|
#define CPMVEC_TIMER3 ((ushort)0x0c) |
|
#define CPMVEC_PIO_PC9 ((ushort)0x0b) |
|
#define CPMVEC_PIO_PC8 ((ushort)0x0a) |
|
#define CPMVEC_PIO_PC7 ((ushort)0x09) |
|
#define CPMVEC_TIMER4 ((ushort)0x07) |
|
#define CPMVEC_PIO_PC6 ((ushort)0x06) |
|
#define CPMVEC_SPI ((ushort)0x05) |
|
#define CPMVEC_SMC1 ((ushort)0x04) |
|
#define CPMVEC_SMC2 ((ushort)0x03) |
|
#define CPMVEC_PIO_PC5 ((ushort)0x02) |
|
#define CPMVEC_PIO_PC4 ((ushort)0x01) |
|
#define CPMVEC_ERROR ((ushort)0x00) |
|
|
|
/* CPM interrupt configuration vector. |
|
*/ |
|
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ |
|
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ |
|
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ |
|
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ |
|
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ |
|
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ |
|
#define CICR_IEN ((uint)0x00000080) /* Int. enable */ |
|
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ |
|
|
|
#define CPM_PIN_INPUT 0 |
|
#define CPM_PIN_OUTPUT 1 |
|
#define CPM_PIN_PRIMARY 0 |
|
#define CPM_PIN_SECONDARY 2 |
|
#define CPM_PIN_GPIO 4 |
|
#define CPM_PIN_OPENDRAIN 8 |
|
#define CPM_PIN_FALLEDGE 16 |
|
#define CPM_PIN_ANYEDGE 0 |
|
|
|
enum cpm_port { |
|
CPM_PORTA, |
|
CPM_PORTB, |
|
CPM_PORTC, |
|
CPM_PORTD, |
|
CPM_PORTE, |
|
}; |
|
|
|
void cpm1_set_pin(enum cpm_port port, int pin, int flags); |
|
|
|
enum cpm_clk_dir { |
|
CPM_CLK_RX, |
|
CPM_CLK_TX, |
|
CPM_CLK_RTX |
|
}; |
|
|
|
enum cpm_clk_target { |
|
CPM_CLK_SCC1, |
|
CPM_CLK_SCC2, |
|
CPM_CLK_SCC3, |
|
CPM_CLK_SCC4, |
|
CPM_CLK_SMC1, |
|
CPM_CLK_SMC2, |
|
}; |
|
|
|
enum cpm_clk { |
|
CPM_BRG1, /* Baud Rate Generator 1 */ |
|
CPM_BRG2, /* Baud Rate Generator 2 */ |
|
CPM_BRG3, /* Baud Rate Generator 3 */ |
|
CPM_BRG4, /* Baud Rate Generator 4 */ |
|
CPM_CLK1, /* Clock 1 */ |
|
CPM_CLK2, /* Clock 2 */ |
|
CPM_CLK3, /* Clock 3 */ |
|
CPM_CLK4, /* Clock 4 */ |
|
CPM_CLK5, /* Clock 5 */ |
|
CPM_CLK6, /* Clock 6 */ |
|
CPM_CLK7, /* Clock 7 */ |
|
CPM_CLK8, /* Clock 8 */ |
|
}; |
|
|
|
int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode); |
|
int cpm1_gpiochip_add16(struct device *dev); |
|
int cpm1_gpiochip_add32(struct device *dev); |
|
|
|
#endif /* __CPM1__ */
|
|
|