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130 lines
3.8 KiB
130 lines
3.8 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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*/ |
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#ifndef _ASM_POWERPC_CACHEFLUSH_H |
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#define _ASM_POWERPC_CACHEFLUSH_H |
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#include <linux/mm.h> |
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#include <asm/cputable.h> |
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#include <asm/cpu_has_feature.h> |
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/* |
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* This flag is used to indicate that the page pointed to by a pte is clean |
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* and does not require cleaning before returning it to the user. |
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*/ |
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#define PG_dcache_clean PG_arch_1 |
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#ifdef CONFIG_PPC_BOOK3S_64 |
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/* |
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* Book3s has no ptesync after setting a pte, so without this ptesync it's |
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* possible for a kernel virtual mapping access to return a spurious fault |
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* if it's accessed right after the pte is set. The page fault handler does |
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* not expect this type of fault. flush_cache_vmap is not exactly the right |
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* place to put this, but it seems to work well enough. |
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*/ |
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static inline void flush_cache_vmap(unsigned long start, unsigned long end) |
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{ |
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asm volatile("ptesync" ::: "memory"); |
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} |
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#define flush_cache_vmap flush_cache_vmap |
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#endif /* CONFIG_PPC_BOOK3S_64 */ |
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
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/* |
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* This is called when a page has been modified by the kernel. |
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* It just marks the page as not i-cache clean. We do the i-cache |
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* flush later when the page is given to a user process, if necessary. |
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*/ |
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static inline void flush_dcache_page(struct page *page) |
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{ |
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if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) |
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return; |
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/* avoid an atomic op if possible */ |
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if (test_bit(PG_dcache_clean, &page->flags)) |
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clear_bit(PG_dcache_clean, &page->flags); |
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} |
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void flush_icache_range(unsigned long start, unsigned long stop); |
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#define flush_icache_range flush_icache_range |
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void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, |
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unsigned long addr, int len); |
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#define flush_icache_user_page flush_icache_user_page |
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void flush_dcache_icache_page(struct page *page); |
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/** |
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* flush_dcache_range(): Write any modified data cache blocks out to memory and |
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* invalidate them. Does not invalidate the corresponding instruction cache |
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* blocks. |
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* |
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* @start: the start address |
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* @stop: the stop address (exclusive) |
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*/ |
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static inline void flush_dcache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long shift = l1_dcache_shift(); |
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unsigned long bytes = l1_dcache_bytes(); |
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void *addr = (void *)(start & ~(bytes - 1)); |
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unsigned long size = stop - (unsigned long)addr + (bytes - 1); |
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unsigned long i; |
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if (IS_ENABLED(CONFIG_PPC64)) |
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mb(); /* sync */ |
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for (i = 0; i < size >> shift; i++, addr += bytes) |
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dcbf(addr); |
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mb(); /* sync */ |
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} |
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/* |
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* Write any modified data cache blocks out to memory. |
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* Does not invalidate the corresponding cache lines (especially for |
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* any corresponding instruction cache). |
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*/ |
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static inline void clean_dcache_range(unsigned long start, unsigned long stop) |
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{ |
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unsigned long shift = l1_dcache_shift(); |
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unsigned long bytes = l1_dcache_bytes(); |
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void *addr = (void *)(start & ~(bytes - 1)); |
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unsigned long size = stop - (unsigned long)addr + (bytes - 1); |
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unsigned long i; |
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for (i = 0; i < size >> shift; i++, addr += bytes) |
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dcbst(addr); |
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mb(); /* sync */ |
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} |
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/* |
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* Like above, but invalidate the D-cache. This is used by the 8xx |
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* to invalidate the cache so the PPC core doesn't get stale data |
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* from the CPM (no cache snooping here :-). |
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*/ |
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static inline void invalidate_dcache_range(unsigned long start, |
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unsigned long stop) |
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{ |
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unsigned long shift = l1_dcache_shift(); |
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unsigned long bytes = l1_dcache_bytes(); |
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void *addr = (void *)(start & ~(bytes - 1)); |
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unsigned long size = stop - (unsigned long)addr + (bytes - 1); |
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unsigned long i; |
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for (i = 0; i < size >> shift; i++, addr += bytes) |
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dcbi(addr); |
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mb(); /* sync */ |
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} |
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#ifdef CONFIG_4xx |
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static inline void flush_instruction_cache(void) |
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{ |
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iccci((void *)KERNELBASE); |
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isync(); |
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} |
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#else |
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void flush_instruction_cache(void); |
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#endif |
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#include <asm-generic/cacheflush.h> |
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#endif /* _ASM_POWERPC_CACHEFLUSH_H */
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