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146 lines
2.8 KiB
146 lines
2.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_POWERPC_CACHE_H |
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#define _ASM_POWERPC_CACHE_H |
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#ifdef __KERNEL__ |
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/* bytes per L1 cache line */ |
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#if defined(CONFIG_PPC_8xx) |
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#define L1_CACHE_SHIFT 4 |
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#define MAX_COPY_PREFETCH 1 |
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#define IFETCH_ALIGN_SHIFT 2 |
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#elif defined(CONFIG_PPC_E500MC) |
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#define L1_CACHE_SHIFT 6 |
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#define MAX_COPY_PREFETCH 4 |
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#define IFETCH_ALIGN_SHIFT 3 |
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#elif defined(CONFIG_PPC32) |
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#define MAX_COPY_PREFETCH 4 |
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#define IFETCH_ALIGN_SHIFT 3 /* 603 fetches 2 insn at a time */ |
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#if defined(CONFIG_PPC_47x) |
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#define L1_CACHE_SHIFT 7 |
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#else |
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#define L1_CACHE_SHIFT 5 |
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#endif |
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#else /* CONFIG_PPC64 */ |
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#define L1_CACHE_SHIFT 7 |
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#define IFETCH_ALIGN_SHIFT 4 /* POWER8,9 */ |
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#endif |
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
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#define SMP_CACHE_BYTES L1_CACHE_BYTES |
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#define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT) |
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#if !defined(__ASSEMBLY__) |
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#ifdef CONFIG_PPC64 |
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struct ppc_cache_info { |
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u32 size; |
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u32 line_size; |
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u32 block_size; /* L1 only */ |
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u32 log_block_size; |
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u32 blocks_per_page; |
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u32 sets; |
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u32 assoc; |
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}; |
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struct ppc64_caches { |
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struct ppc_cache_info l1d; |
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struct ppc_cache_info l1i; |
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struct ppc_cache_info l2; |
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struct ppc_cache_info l3; |
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}; |
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extern struct ppc64_caches ppc64_caches; |
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static inline u32 l1_dcache_shift(void) |
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{ |
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return ppc64_caches.l1d.log_block_size; |
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} |
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static inline u32 l1_dcache_bytes(void) |
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{ |
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return ppc64_caches.l1d.block_size; |
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} |
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static inline u32 l1_icache_shift(void) |
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{ |
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return ppc64_caches.l1i.log_block_size; |
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} |
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static inline u32 l1_icache_bytes(void) |
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{ |
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return ppc64_caches.l1i.block_size; |
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} |
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#else |
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static inline u32 l1_dcache_shift(void) |
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{ |
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return L1_CACHE_SHIFT; |
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} |
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static inline u32 l1_dcache_bytes(void) |
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{ |
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return L1_CACHE_BYTES; |
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} |
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static inline u32 l1_icache_shift(void) |
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{ |
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return L1_CACHE_SHIFT; |
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} |
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static inline u32 l1_icache_bytes(void) |
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{ |
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return L1_CACHE_BYTES; |
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} |
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#endif |
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#define __read_mostly __section(".data..read_mostly") |
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#ifdef CONFIG_PPC_BOOK3S_32 |
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extern long _get_L2CR(void); |
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extern long _get_L3CR(void); |
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extern void _set_L2CR(unsigned long); |
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extern void _set_L3CR(unsigned long); |
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#else |
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#define _get_L2CR() 0L |
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#define _get_L3CR() 0L |
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#define _set_L2CR(val) do { } while(0) |
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#define _set_L3CR(val) do { } while(0) |
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#endif |
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static inline void dcbz(void *addr) |
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{ |
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__asm__ __volatile__ ("dcbz 0, %0" : : "r"(addr) : "memory"); |
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} |
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static inline void dcbi(void *addr) |
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{ |
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__asm__ __volatile__ ("dcbi 0, %0" : : "r"(addr) : "memory"); |
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} |
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static inline void dcbf(void *addr) |
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{ |
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__asm__ __volatile__ ("dcbf 0, %0" : : "r"(addr) : "memory"); |
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} |
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static inline void dcbst(void *addr) |
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{ |
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__asm__ __volatile__ ("dcbst 0, %0" : : "r"(addr) : "memory"); |
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} |
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static inline void icbi(void *addr) |
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{ |
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asm volatile ("icbi 0, %0" : : "r"(addr) : "memory"); |
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} |
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static inline void iccci(void *addr) |
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{ |
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asm volatile ("iccci 0, %0" : : "r"(addr) : "memory"); |
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} |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_POWERPC_CACHE_H */
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