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463 lines
10 KiB
463 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* MPC8360E RDK Device Tree Source |
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* |
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* Copyright 2006 Freescale Semiconductor Inc. |
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* Copyright 2007-2008 MontaVista Software, Inc. |
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* |
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* Author: Anton Vorontsov <[email protected]> |
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*/ |
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/dts-v1/; |
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/ { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8360rdk"; |
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aliases { |
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serial0 = &serial0; |
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serial1 = &serial1; |
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serial2 = &serial2; |
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serial3 = &serial3; |
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ethernet0 = &enet0; |
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ethernet1 = &enet1; |
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ethernet2 = &enet2; |
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ethernet3 = &enet3; |
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pci0 = &pci0; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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PowerPC,8360@0 { |
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device_type = "cpu"; |
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reg = <0>; |
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d-cache-line-size = <32>; |
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i-cache-line-size = <32>; |
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d-cache-size = <32768>; |
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i-cache-size = <32768>; |
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/* filled by u-boot */ |
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timebase-frequency = <0>; |
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bus-frequency = <0>; |
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clock-frequency = <0>; |
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}; |
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}; |
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memory { |
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device_type = "memory"; |
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/* filled by u-boot */ |
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reg = <0 0>; |
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}; |
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soc@e0000000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "soc"; |
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compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc", |
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"simple-bus"; |
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ranges = <0 0xe0000000 0x200000>; |
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reg = <0xe0000000 0x200>; |
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/* filled by u-boot */ |
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bus-frequency = <0>; |
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wdt@200 { |
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compatible = "mpc83xx_wdt"; |
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reg = <0x200 0x100>; |
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}; |
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pmc: power@b00 { |
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compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; |
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reg = <0xb00 0x100 0xa00 0x100>; |
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interrupts = <80 0x8>; |
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interrupt-parent = <&ipic>; |
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}; |
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i2c@3000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <0>; |
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compatible = "fsl-i2c"; |
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reg = <0x3000 0x100>; |
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interrupts = <14 8>; |
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interrupt-parent = <&ipic>; |
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dfsrr; |
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}; |
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i2c@3100 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cell-index = <1>; |
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compatible = "fsl-i2c"; |
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reg = <0x3100 0x100>; |
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interrupts = <16 8>; |
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interrupt-parent = <&ipic>; |
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dfsrr; |
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}; |
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serial0: serial@4500 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550"; |
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reg = <0x4500 0x100>; |
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interrupts = <9 8>; |
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interrupt-parent = <&ipic>; |
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/* filled by u-boot */ |
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clock-frequency = <0>; |
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}; |
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serial1: serial@4600 { |
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device_type = "serial"; |
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compatible = "fsl,ns16550", "ns16550"; |
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reg = <0x4600 0x100>; |
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interrupts = <10 8>; |
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interrupt-parent = <&ipic>; |
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/* filled by u-boot */ |
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clock-frequency = <0>; |
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}; |
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dma@82a8 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8360-dma", "fsl,elo-dma"; |
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reg = <0x82a8 4>; |
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ranges = <0 0x8100 0x1a8>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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cell-index = <0>; |
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dma-channel@0 { |
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0 0x80>; |
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cell-index = <0>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@80 { |
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x80 0x80>; |
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cell-index = <1>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@100 { |
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x100 0x80>; |
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cell-index = <2>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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dma-channel@180 { |
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel"; |
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reg = <0x180 0x28>; |
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cell-index = <3>; |
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interrupt-parent = <&ipic>; |
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interrupts = <71 8>; |
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}; |
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}; |
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crypto@30000 { |
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compatible = "fsl,sec2.0"; |
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reg = <0x30000 0x10000>; |
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interrupts = <11 0x8>; |
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interrupt-parent = <&ipic>; |
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fsl,num-channels = <4>; |
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fsl,channel-fifo-len = <24>; |
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fsl,exec-units-mask = <0x7e>; |
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fsl,descriptor-types-mask = <0x01010ebf>; |
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sleep = <&pmc 0x03000000>; |
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}; |
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ipic: interrupt-controller@700 { |
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#address-cells = <0>; |
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#interrupt-cells = <2>; |
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compatible = "fsl,pq2pro-pic", "fsl,ipic"; |
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interrupt-controller; |
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reg = <0x700 0x100>; |
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}; |
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qe_pio_b: gpio-controller@1418 { |
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#gpio-cells = <2>; |
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compatible = "fsl,mpc8360-qe-pario-bank", |
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"fsl,mpc8323-qe-pario-bank"; |
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reg = <0x1418 0x18>; |
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gpio-controller; |
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}; |
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qe_pio_e: gpio-controller@1460 { |
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#gpio-cells = <2>; |
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compatible = "fsl,mpc8360-qe-pario-bank", |
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"fsl,mpc8323-qe-pario-bank"; |
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reg = <0x1460 0x18>; |
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gpio-controller; |
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}; |
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qe@100000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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device_type = "qe"; |
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compatible = "fsl,qe", "simple-bus"; |
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ranges = <0 0x100000 0x100000>; |
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reg = <0x100000 0x480>; |
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/* filled by u-boot */ |
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clock-frequency = <0>; |
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bus-frequency = <0>; |
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brg-frequency = <0>; |
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fsl,qe-num-riscs = <2>; |
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fsl,qe-num-snums = <28>; |
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muram@10000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
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ranges = <0 0x10000 0xc000>; |
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data-only@0 { |
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compatible = "fsl,qe-muram-data", |
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"fsl,cpm-muram-data"; |
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reg = <0 0xc000>; |
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}; |
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}; |
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timer@440 { |
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compatible = "fsl,mpc8360-qe-gtm", |
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"fsl,qe-gtm", "fsl,gtm"; |
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reg = <0x440 0x40>; |
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interrupts = <12 13 14 15>; |
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interrupt-parent = <&qeic>; |
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clock-frequency = <166666666>; |
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}; |
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usb@6c0 { |
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compatible = "fsl,mpc8360-qe-usb", |
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"fsl,mpc8323-qe-usb"; |
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reg = <0x6c0 0x40 0x8b00 0x100>; |
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interrupts = <11>; |
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interrupt-parent = <&qeic>; |
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fsl,fullspeed-clock = "clk21"; |
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gpios = <&qe_pio_b 2 0 /* USBOE */ |
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&qe_pio_b 3 0 /* USBTP */ |
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&qe_pio_b 8 0 /* USBTN */ |
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&qe_pio_b 9 0 /* USBRP */ |
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&qe_pio_b 11 0 /* USBRN */ |
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&qe_pio_e 20 0 /* SPEED */ |
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&qe_pio_e 21 1 /* POWER */>; |
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}; |
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spi@4c0 { |
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cell-index = <0>; |
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compatible = "fsl,spi"; |
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reg = <0x4c0 0x40>; |
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interrupts = <2>; |
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interrupt-parent = <&qeic>; |
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mode = "cpu-qe"; |
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}; |
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spi@500 { |
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cell-index = <1>; |
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compatible = "fsl,spi"; |
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reg = <0x500 0x40>; |
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interrupts = <1>; |
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interrupt-parent = <&qeic>; |
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mode = "cpu-qe"; |
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}; |
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enet0: ucc@2000 { |
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device_type = "network"; |
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compatible = "ucc_geth"; |
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cell-index = <1>; |
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reg = <0x2000 0x200>; |
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interrupts = <32>; |
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interrupt-parent = <&qeic>; |
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rx-clock-name = "none"; |
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tx-clock-name = "clk9"; |
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phy-handle = <&phy2>; |
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phy-connection-type = "rgmii-rxid"; |
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/* filled by u-boot */ |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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}; |
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enet1: ucc@3000 { |
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device_type = "network"; |
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compatible = "ucc_geth"; |
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cell-index = <2>; |
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reg = <0x3000 0x200>; |
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interrupts = <33>; |
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interrupt-parent = <&qeic>; |
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rx-clock-name = "none"; |
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tx-clock-name = "clk4"; |
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phy-handle = <&phy4>; |
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phy-connection-type = "rgmii-rxid"; |
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/* filled by u-boot */ |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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}; |
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enet2: ucc@2600 { |
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device_type = "network"; |
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compatible = "ucc_geth"; |
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cell-index = <7>; |
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reg = <0x2600 0x200>; |
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interrupts = <42>; |
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interrupt-parent = <&qeic>; |
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rx-clock-name = "clk20"; |
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tx-clock-name = "clk19"; |
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phy-handle = <&phy1>; |
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phy-connection-type = "mii"; |
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/* filled by u-boot */ |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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}; |
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enet3: ucc@3200 { |
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device_type = "network"; |
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compatible = "ucc_geth"; |
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cell-index = <4>; |
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reg = <0x3200 0x200>; |
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interrupts = <35>; |
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interrupt-parent = <&qeic>; |
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rx-clock-name = "clk8"; |
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tx-clock-name = "clk7"; |
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phy-handle = <&phy3>; |
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phy-connection-type = "mii"; |
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/* filled by u-boot */ |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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}; |
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mdio@2120 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,ucc-mdio"; |
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reg = <0x2120 0x18>; |
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phy1: ethernet-phy@1 { |
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compatible = "national,DP83848VV"; |
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reg = <1>; |
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}; |
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phy2: ethernet-phy@2 { |
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compatible = "broadcom,BCM5481UA2KMLG"; |
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reg = <2>; |
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}; |
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phy3: ethernet-phy@3 { |
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compatible = "national,DP83848VV"; |
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reg = <3>; |
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}; |
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phy4: ethernet-phy@4 { |
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compatible = "broadcom,BCM5481UA2KMLG"; |
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reg = <4>; |
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}; |
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}; |
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serial2: ucc@2400 { |
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device_type = "serial"; |
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compatible = "ucc_uart"; |
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reg = <0x2400 0x200>; |
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cell-index = <5>; |
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port-number = <0>; |
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rx-clock-name = "brg7"; |
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tx-clock-name = "brg8"; |
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interrupts = <40>; |
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interrupt-parent = <&qeic>; |
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soft-uart; |
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}; |
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serial3: ucc@3400 { |
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device_type = "serial"; |
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compatible = "ucc_uart"; |
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reg = <0x3400 0x200>; |
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cell-index = <6>; |
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port-number = <1>; |
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rx-clock-name = "brg13"; |
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tx-clock-name = "brg14"; |
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interrupts = <41>; |
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interrupt-parent = <&qeic>; |
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soft-uart; |
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}; |
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qeic: interrupt-controller@80 { |
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#address-cells = <0>; |
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#interrupt-cells = <1>; |
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compatible = "fsl,qe-ic"; |
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interrupt-controller; |
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reg = <0x80 0x80>; |
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big-endian; |
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interrupts = <32 8 33 8>; |
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interrupt-parent = <&ipic>; |
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}; |
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}; |
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}; |
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localbus@e0005000 { |
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#address-cells = <2>; |
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#size-cells = <1>; |
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compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", |
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"simple-bus"; |
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reg = <0xe0005000 0xd8>; |
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ranges = <0 0 0xff800000 0x0800000 |
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1 0 0x60000000 0x0001000 |
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2 0 0x70000000 0x4000000>; |
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flash@0,0 { |
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compatible = "intel,PC28F640P30T85", "cfi-flash"; |
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reg = <0 0 0x800000>; |
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bank-width = <2>; |
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device-width = <1>; |
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}; |
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upm@1,0 { |
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compatible = "fsl,upm-nand"; |
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reg = <1 0 1>; |
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fsl,upm-addr-offset = <16>; |
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fsl,upm-cmd-offset = <8>; |
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gpios = <&qe_pio_e 18 0>; |
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flash { |
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compatible = "st,nand512-a"; |
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}; |
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}; |
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display@2,0 { |
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device_type = "display"; |
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compatible = "fujitsu,MB86277", "fujitsu,mint"; |
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reg = <2 0 0x4000000>; |
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fujitsu,sh3; |
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little-endian; |
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/* filled by u-boot */ |
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address = <0>; |
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depth = <0>; |
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width = <0>; |
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height = <0>; |
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linebytes = <0>; |
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/* linux,opened; - added by uboot */ |
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}; |
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}; |
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pci0: pci@e0008500 { |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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device_type = "pci"; |
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compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci"; |
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reg = <0xe0008500 0x100 /* internal registers */ |
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0xe0008300 0x8>; /* config space access registers */ |
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ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000 |
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0x42000000 0 0x80000000 0x80000000 0 0x10000000 |
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0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>; |
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interrupts = <66 8>; |
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interrupt-parent = <&ipic>; |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */ |
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0xa000 0 0 1 &ipic 18 8 |
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0xa000 0 0 2 &ipic 19 8 |
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/* PCI1 IDSEL 0x15 AD21 */ |
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0xa800 0 0 1 &ipic 19 8 |
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0xa800 0 0 2 &ipic 20 8 |
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0xa800 0 0 3 &ipic 21 8 |
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0xa800 0 0 4 &ipic 18 8>; |
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sleep = <&pmc 0x00010000>; |
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/* filled by u-boot */ |
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bus-range = <0 0>; |
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clock-frequency = <0>; |
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}; |
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};
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