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117 lines
3.3 KiB
117 lines
3.3 KiB
/* |
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* P5020/P5010 Silicon/SoC Device Tree Source (pre include) |
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* |
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* Copyright 2011 - 2015 Freescale Semiconductor Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/dts-v1/; |
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/include/ "e5500_power_isa.dtsi" |
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/ { |
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compatible = "fsl,P5020"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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aliases { |
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ccsr = &soc; |
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dcsr = &dcsr; |
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serial0 = &serial0; |
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serial1 = &serial1; |
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serial2 = &serial2; |
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serial3 = &serial3; |
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pci0 = &pci0; |
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pci1 = &pci1; |
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pci2 = &pci2; |
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pci3 = &pci3; |
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usb0 = &usb0; |
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usb1 = &usb1; |
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dma0 = &dma0; |
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dma1 = &dma1; |
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sdhc = &sdhc; |
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msi0 = &msi0; |
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msi1 = &msi1; |
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msi2 = &msi2; |
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crypto = &crypto; |
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sec_jr0 = &sec_jr0; |
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sec_jr1 = &sec_jr1; |
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sec_jr2 = &sec_jr2; |
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sec_jr3 = &sec_jr3; |
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rtic_a = &rtic_a; |
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rtic_b = &rtic_b; |
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rtic_c = &rtic_c; |
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rtic_d = &rtic_d; |
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sec_mon = &sec_mon; |
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raideng = &raideng; |
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raideng_jr0 = &raideng_jr0; |
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raideng_jr1 = &raideng_jr1; |
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raideng_jr2 = &raideng_jr2; |
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raideng_jr3 = &raideng_jr3; |
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fman0 = &fman0; |
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ethernet0 = &enet0; |
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ethernet1 = &enet1; |
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ethernet2 = &enet2; |
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ethernet3 = &enet3; |
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ethernet4 = &enet4; |
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ethernet5 = &enet5; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: PowerPC,e5500@0 { |
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device_type = "cpu"; |
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reg = <0>; |
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clocks = <&clockgen 1 0>; |
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next-level-cache = <&L2_0>; |
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fsl,portid-mapping = <0x80000000>; |
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L2_0: l2-cache { |
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next-level-cache = <&cpc>; |
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}; |
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}; |
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cpu1: PowerPC,e5500@1 { |
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device_type = "cpu"; |
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reg = <1>; |
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clocks = <&clockgen 1 1>; |
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next-level-cache = <&L2_1>; |
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fsl,portid-mapping = <0x40000000>; |
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L2_1: l2-cache { |
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next-level-cache = <&cpc>; |
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}; |
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}; |
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}; |
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};
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