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439 lines
9.0 KiB
439 lines
9.0 KiB
/* |
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* P4080DS Device Tree Source |
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* |
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* Copyright 2009 - 2015 Freescale Semiconductor Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY |
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY |
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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/include/ "p4080si-pre.dtsi" |
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/ { |
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model = "fsl,P4080DS"; |
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compatible = "fsl,P4080DS"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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aliases { |
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phy_rgmii = &phyrgmii; |
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phy5_slot3 = &phy5slot3; |
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phy6_slot3 = &phy6slot3; |
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phy7_slot3 = &phy7slot3; |
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phy8_slot3 = &phy8slot3; |
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emi1_slot3 = &p4080mdio2; |
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emi1_slot4 = &p4080mdio1; |
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emi1_slot5 = &p4080mdio3; |
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emi1_rgmii = &p4080mdio0; |
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emi2_slot4 = &p4080xmdio1; |
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emi2_slot5 = &p4080xmdio3; |
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}; |
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memory { |
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device_type = "memory"; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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bman_fbpr: bman-fbpr { |
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size = <0 0x1000000>; |
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alignment = <0 0x1000000>; |
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}; |
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qman_fqd: qman-fqd { |
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size = <0 0x400000>; |
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alignment = <0 0x400000>; |
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}; |
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qman_pfdr: qman-pfdr { |
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size = <0 0x2000000>; |
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alignment = <0 0x2000000>; |
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}; |
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}; |
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dcsr: dcsr@f00000000 { |
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ranges = <0x00000000 0xf 0x00000000 0x01008000>; |
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}; |
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bportals: bman-portals@ff4000000 { |
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ranges = <0x0 0xf 0xf4000000 0x200000>; |
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}; |
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qportals: qman-portals@ff4200000 { |
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ranges = <0x0 0xf 0xf4200000 0x200000>; |
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}; |
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soc: soc@ffe000000 { |
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
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reg = <0xf 0xfe000000 0 0x00001000>; |
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spi@110000 { |
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flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spansion,s25sl12801", "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <40000000>; /* input clock */ |
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partition@u-boot { |
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label = "u-boot"; |
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reg = <0x00000000 0x00100000>; |
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read-only; |
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}; |
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partition@kernel { |
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label = "kernel"; |
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reg = <0x00100000 0x00500000>; |
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read-only; |
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}; |
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partition@dtb { |
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label = "dtb"; |
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reg = <0x00600000 0x00100000>; |
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read-only; |
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}; |
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partition@fs { |
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label = "file system"; |
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reg = <0x00700000 0x00900000>; |
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}; |
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}; |
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}; |
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i2c@118100 { |
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eeprom@51 { |
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compatible = "atmel,spd"; |
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reg = <0x51>; |
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}; |
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eeprom@52 { |
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compatible = "atmel,spd"; |
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reg = <0x52>; |
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}; |
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rtc@68 { |
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compatible = "dallas,ds3232"; |
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reg = <0x68>; |
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interrupts = <0x1 0x1 0 0>; |
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}; |
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adt7461@4c { |
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compatible = "adi,adt7461"; |
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reg = <0x4c>; |
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}; |
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}; |
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i2c@118000 { |
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zl2006@21 { |
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compatible = "zl2006"; |
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reg = <0x21>; |
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}; |
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zl2006@22 { |
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compatible = "zl2006"; |
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reg = <0x22>; |
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}; |
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zl2006@23 { |
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compatible = "zl2006"; |
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reg = <0x23>; |
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}; |
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zl2006@24 { |
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compatible = "zl2006"; |
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reg = <0x24>; |
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}; |
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eeprom@50 { |
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compatible = "atmel,24c64"; |
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reg = <0x50>; |
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}; |
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eeprom@55 { |
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compatible = "atmel,24c64"; |
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reg = <0x55>; |
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}; |
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eeprom@56 { |
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compatible = "atmel,24c64"; |
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reg = <0x56>; |
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}; |
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eeprom@57 { |
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compatible = "atmel,24c02"; |
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reg = <0x57>; |
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}; |
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}; |
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i2c@119100 { |
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/* 0x6E: ICS9FG108 */ |
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}; |
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usb0: usb@210000 { |
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phy_type = "ulpi"; |
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}; |
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usb1: usb@211000 { |
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dr_mode = "host"; |
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phy_type = "ulpi"; |
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}; |
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fman@400000 { |
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ethernet@e0000 { |
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phy-handle = <&phy0>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e2000 { |
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phy-handle = <&phy1>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e4000 { |
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phy-handle = <&phy2>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e6000 { |
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phy-handle = <&phy3>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@f0000 { |
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phy-handle = <&phy10>; |
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phy-connection-type = "xgmii"; |
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}; |
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}; |
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fman@500000 { |
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ethernet@e0000 { |
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phy-handle = <&phy5>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e2000 { |
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phy-handle = <&phy6>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e4000 { |
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phy-handle = <&phy7>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@e6000 { |
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phy-handle = <&phy8>; |
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phy-connection-type = "sgmii"; |
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}; |
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ethernet@f0000 { |
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phy-handle = <&phy11>; |
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phy-connection-type = "xgmii"; |
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}; |
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}; |
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}; |
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rio: rapidio@ffe0c0000 { |
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reg = <0xf 0xfe0c0000 0 0x11000>; |
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port1 { |
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ranges = <0 0 0xc 0x20000000 0 0x10000000>; |
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}; |
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port2 { |
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ranges = <0 0 0xc 0x30000000 0 0x10000000>; |
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}; |
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}; |
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lbc: localbus@ffe124000 { |
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reg = <0xf 0xfe124000 0 0x1000>; |
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ranges = <0 0 0xf 0xe8000000 0x08000000 |
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3 0 0xf 0xffdf0000 0x00008000>; |
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flash@0,0 { |
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compatible = "cfi-flash"; |
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reg = <0 0 0x08000000>; |
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bank-width = <2>; |
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device-width = <2>; |
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}; |
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board-control@3,0 { |
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compatible = "fsl,p4080ds-fpga", "fsl,fpga-ngpixis"; |
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reg = <3 0 0x30>; |
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}; |
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}; |
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pci0: pcie@ffe200000 { |
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reg = <0xf 0xfe200000 0 0x1000>; |
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ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
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0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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pci1: pcie@ffe201000 { |
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reg = <0xf 0xfe201000 0 0x1000>; |
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ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
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0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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pci2: pcie@ffe202000 { |
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reg = <0xf 0xfe202000 0 0x1000>; |
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ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 |
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0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
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pcie@0 { |
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ranges = <0x02000000 0 0xe0000000 |
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0x02000000 0 0xe0000000 |
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0 0x20000000 |
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0x01000000 0 0x00000000 |
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0x01000000 0 0x00000000 |
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0 0x00010000>; |
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}; |
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}; |
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mdio-mux-emi1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "mdio-mux-gpio", "mdio-mux"; |
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mdio-parent-bus = <&mdio0>; |
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gpios = <&gpio0 1 0>, <&gpio0 0 0>; |
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p4080mdio0: mdio@0 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0>; |
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phyrgmii: ethernet-phy@0 { |
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reg = <0x0>; |
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}; |
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}; |
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p4080mdio1: mdio@1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <1>; |
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phy5: ethernet-phy@1c { |
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reg = <0x1c>; |
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}; |
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phy6: ethernet-phy@1d { |
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reg = <0x1d>; |
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}; |
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phy7: ethernet-phy@1e { |
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reg = <0x1e>; |
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}; |
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phy8: ethernet-phy@1f { |
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reg = <0x1f>; |
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}; |
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}; |
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p4080mdio2: mdio@2 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <2>; |
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status = "disabled"; |
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phy5slot3: ethernet-phy@1c { |
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reg = <0x1c>; |
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}; |
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phy6slot3: ethernet-phy@1d { |
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reg = <0x1d>; |
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}; |
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phy7slot3: ethernet-phy@1e { |
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reg = <0x1e>; |
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}; |
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phy8slot3: ethernet-phy@1f { |
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reg = <0x1f>; |
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}; |
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}; |
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p4080mdio3: mdio@3 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <3>; |
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phy0: ethernet-phy@1c { |
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reg = <0x1c>; |
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}; |
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phy1: ethernet-phy@1d { |
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reg = <0x1d>; |
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}; |
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phy2: ethernet-phy@1e { |
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reg = <0x1e>; |
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}; |
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phy3: ethernet-phy@1f { |
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reg = <0x1f>; |
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}; |
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}; |
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}; |
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mdio-mux-emi2 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "mdio-mux-gpio", "mdio-mux"; |
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mdio-parent-bus = <&xmdio0>; |
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gpios = <&gpio0 3 0>, <&gpio0 2 0>; |
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p4080xmdio1: mdio@1 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <1>; |
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phy11: ethernet-phy@0 { |
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compatible = "ethernet-phy-ieee802.3-c45"; |
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reg = <0x0>; |
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}; |
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}; |
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p4080xmdio3: mdio@3 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <3>; |
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phy10: ethernet-phy@4 { |
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compatible = "ethernet-phy-ieee802.3-c45"; |
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reg = <0x4>; |
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}; |
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}; |
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}; |
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}; |
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/include/ "p4080si-post.dtsi"
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