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85 lines
2.7 KiB
85 lines
2.7 KiB
/* |
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* B4420 Silicon/SoC Device Tree Source (pre include) |
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* |
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* Copyright 2012 - 2015 Freescale Semiconductor, Inc. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in the |
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* documentation and/or other materials provided with the distribution. |
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* * Neither the name of Freescale Semiconductor nor the |
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* names of its contributors may be used to endorse or promote products |
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* derived from this software without specific prior written permission. |
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* |
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* |
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* ALTERNATIVELY, this software may be distributed under the terms of the |
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* GNU General Public License ("GPL") as published by the Free Software |
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* Foundation, either version 2 of that License or (at your option) any |
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* later version. |
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* |
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* This software is provided by Freescale Semiconductor "as is" and any |
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* express or implied warranties, including, but not limited to, the implied |
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* warranties of merchantability and fitness for a particular purpose are |
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* disclaimed. In no event shall Freescale Semiconductor be liable for any |
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* direct, indirect, incidental, special, exemplary, or consequential damages |
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* (including, but not limited to, procurement of substitute goods or services; |
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* loss of use, data, or profits; or business interruption) however caused and |
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* on any theory of liability, whether in contract, strict liability, or tort |
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* (including negligence or otherwise) arising in any way out of the use of |
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* this software, even if advised of the possibility of such damage. |
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*/ |
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/dts-v1/; |
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/include/ "e6500_power_isa.dtsi" |
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/ { |
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compatible = "fsl,B4420"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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interrupt-parent = <&mpic>; |
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aliases { |
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ccsr = &soc; |
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dcsr = &dcsr; |
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serial0 = &serial0; |
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serial1 = &serial1; |
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serial2 = &serial2; |
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serial3 = &serial3; |
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pci0 = &pci0; |
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usb0 = &usb0; |
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dma0 = &dma0; |
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dma1 = &dma1; |
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sdhc = &sdhc; |
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fman0 = &fman0; |
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ethernet0 = &enet0; |
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ethernet1 = &enet1; |
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ethernet2 = &enet2; |
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ethernet3 = &enet3; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: PowerPC,e6500@0 { |
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device_type = "cpu"; |
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reg = <0 1>; |
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clocks = <&clockgen 1 0>; |
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next-level-cache = <&L2_1>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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cpu1: PowerPC,e6500@2 { |
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device_type = "cpu"; |
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reg = <2 3>; |
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clocks = <&clockgen 1 0>; |
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next-level-cache = <&L2_1>; |
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fsl,portid-mapping = <0x80000000>; |
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}; |
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}; |
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};
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