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47 lines
1.7 KiB
47 lines
1.7 KiB
GPIO assisted NAND flash |
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The GPIO assisted NAND flash uses a memory mapped interface to |
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read/write the NAND commands and data and GPIO pins for the control |
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signals. |
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Required properties: |
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- compatible : "gpio-control-nand" |
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- reg : should specify localbus chip select and size used for the chip. The |
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resource describes the data bus connected to the NAND flash and all accesses |
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are made in native endianness. |
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- #address-cells, #size-cells : Must be present if the device has sub-nodes |
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representing partitions. |
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- gpios : Specifies the GPIO pins to control the NAND device. The order of |
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GPIO references is: RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional. |
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Optional properties: |
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- bank-width : Width (in bytes) of the device. If not present, the width |
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defaults to 1 byte. |
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- chip-delay : chip dependent delay for transferring data from array to |
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read registers (tR). If not present then a default of 20us is used. |
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- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read |
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location used to guard against bus reordering with regards to accesses to |
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the GPIO's and the NAND flash data bus. If present, then after changing |
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GPIO state and before and after command byte writes, this register will be |
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read to ensure that the GPIO accesses have completed. |
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The device tree may optionally contain sub-nodes describing partitions of the |
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address space. See partition.txt for more detail. |
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Examples: |
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gpio-nand@1,0 { |
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compatible = "gpio-control-nand"; |
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reg = <1 0x0000 0x2>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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gpios = <&banka 1 0>, /* RDY */ |
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<0>, /* nCE */ |
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<&banka 3 0>, /* ALE */ |
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<&banka 4 0>, /* CLE */ |
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<0>; /* nWP */ |
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partition@0 { |
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... |
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}; |
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};
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