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174 lines
5.7 KiB
174 lines
5.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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# Copyright (C) 2020 Texas Instruments Incorporated |
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# Author: Peter Ujfalusi <[email protected]> |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/ti/k3-pktdma.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Texas Instruments K3 DMSS PKTDMA Device Tree Bindings |
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maintainers: |
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- Peter Ujfalusi <[email protected]> |
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description: | |
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The Packet DMA (PKTDMA) is intended to perform similar functions as the packet |
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mode channels of K3 UDMA-P. |
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PKTDMA only includes Split channels to service PSI-L based peripherals. |
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The peripherals can be PSI-L native or legacy, non PSI-L native peripherals |
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with PDMAs. PDMA is tasked to act as a bridge between the PSI-L fabric and the |
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legacy peripheral. |
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PDMAs can be configured via PKTDMA split channel's peer registers to match |
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with the configuration of the legacy peripheral. |
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allOf: |
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- $ref: /schemas/dma/dma-controller.yaml# |
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properties: |
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compatible: |
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const: ti,am64-dmss-pktdma |
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"#dma-cells": |
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const: 2 |
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description: | |
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The first cell is the PSI-L thread ID of the remote (to PKTDMA) end. |
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Valid ranges for thread ID depends on the data movement direction: |
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for source thread IDs (rx): 0 - 0x7fff |
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for destination thread IDs (tx): 0x8000 - 0xffff |
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Please refer to the device documentation for the PSI-L thread map and also |
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the PSI-L peripheral chapter for the correct thread ID. |
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The second cell is the ASEL value for the channel |
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reg: |
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maxItems: 4 |
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reg-names: |
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items: |
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- const: gcfg |
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- const: rchanrt |
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- const: tchanrt |
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- const: ringrt |
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msi-parent: true |
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ti,sci-rm-range-tchan: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Array of PKTDMA split tx channel resource subtypes for resource allocation |
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for this host |
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minItems: 1 |
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# Should be enough |
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maxItems: 255 |
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items: |
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maximum: 0x3f |
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ti,sci-rm-range-tflow: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Array of PKTDMA split tx flow resource subtypes for resource allocation |
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for this host |
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minItems: 1 |
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# Should be enough |
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maxItems: 255 |
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items: |
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maximum: 0x3f |
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ti,sci-rm-range-rchan: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Array of PKTDMA split rx channel resource subtypes for resource allocation |
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for this host |
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minItems: 1 |
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# Should be enough |
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maxItems: 255 |
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items: |
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maximum: 0x3f |
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ti,sci-rm-range-rflow: |
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$ref: /schemas/types.yaml#/definitions/uint32-array |
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description: | |
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Array of PKTDMA split rx flow resource subtypes for resource allocation |
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for this host |
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minItems: 1 |
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# Should be enough |
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maxItems: 255 |
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items: |
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maximum: 0x3f |
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required: |
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- compatible |
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- "#dma-cells" |
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- reg |
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- reg-names |
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- msi-parent |
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- ti,sci |
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- ti,sci-dev-id |
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- ti,sci-rm-range-tchan |
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- ti,sci-rm-range-tflow |
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- ti,sci-rm-range-rchan |
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- ti,sci-rm-range-rflow |
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unevaluatedProperties: false |
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examples: |
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- |+ |
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cbass_main { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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main_dmss { |
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compatible = "simple-mfd"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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dma-ranges; |
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ranges; |
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ti,sci-dev-id = <25>; |
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main_pktdma: dma-controller@485c0000 { |
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compatible = "ti,am64-dmss-pktdma"; |
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reg = <0x0 0x485c0000 0x0 0x100>, |
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<0x0 0x4a800000 0x0 0x20000>, |
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<0x0 0x4aa00000 0x0 0x40000>, |
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<0x0 0x4b800000 0x0 0x400000>; |
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reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; |
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msi-parent = <&inta_main_dmss>; |
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#dma-cells = <2>; |
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ti,sci = <&dmsc>; |
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ti,sci-dev-id = <30>; |
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ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ |
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<0x24>, /* CPSW_TX_CHAN */ |
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<0x25>, /* SAUL_TX_0_CHAN */ |
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<0x26>, /* SAUL_TX_1_CHAN */ |
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<0x27>, /* ICSSG_0_TX_CHAN */ |
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<0x28>; /* ICSSG_1_TX_CHAN */ |
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ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ |
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<0x11>, /* RING_CPSW_TX_CHAN */ |
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<0x12>, /* RING_SAUL_TX_0_CHAN */ |
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<0x13>, /* RING_SAUL_TX_1_CHAN */ |
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<0x14>, /* RING_ICSSG_0_TX_CHAN */ |
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<0x15>; /* RING_ICSSG_1_TX_CHAN */ |
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ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ |
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<0x2b>, /* CPSW_RX_CHAN */ |
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<0x2d>, /* SAUL_RX_0_CHAN */ |
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<0x2f>, /* SAUL_RX_1_CHAN */ |
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<0x31>, /* SAUL_RX_2_CHAN */ |
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<0x33>, /* SAUL_RX_3_CHAN */ |
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<0x35>, /* ICSSG_0_RX_CHAN */ |
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<0x37>; /* ICSSG_1_RX_CHAN */ |
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ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ |
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<0x2c>, /* FLOW_CPSW_RX_CHAN */ |
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<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ |
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<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ |
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<0x36>, /* FLOW_ICSSG_0_RX_CHAN */ |
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<0x38>; /* FLOW_ICSSG_1_RX_CHAN */ |
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}; |
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}; |
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};
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