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61 lines
1.3 KiB
61 lines
1.3 KiB
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Altera mSGDMA IP core |
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maintainers: |
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- Olivier Dautricourt <[email protected]> |
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description: | |
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Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) |
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intellectual property (IP) |
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allOf: |
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- $ref: "dma-controller.yaml#" |
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properties: |
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compatible: |
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const: altr,socfpga-msgdma |
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reg: |
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items: |
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- description: Control and Status Register Slave Port |
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- description: Descriptor Slave Port |
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- description: Response Slave Port |
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reg-names: |
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items: |
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- const: csr |
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- const: desc |
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- const: resp |
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interrupts: |
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maxItems: 1 |
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"#dma-cells": |
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const: 1 |
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description: |
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The cell identifies the channel id (must be 0) |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- interrupts |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/irq.h> |
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msgdma_controller: dma-controller@ff200b00 { |
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compatible = "altr,socfpga-msgdma"; |
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reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>; |
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reg-names = "csr", "desc", "resp"; |
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
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#dma-cells = <1>; |
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};
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