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249 lines
7.7 KiB
249 lines
7.7 KiB
Qualcomm Technologies Inc. adreno/snapdragon DSI output |
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DSI Controller: |
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Required properties: |
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- compatible: |
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* "qcom,mdss-dsi-ctrl" |
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- reg: Physical base address and length of the registers of controller |
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- reg-names: The names of register regions. The following regions are required: |
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* "dsi_ctrl" |
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- interrupts: The interrupt signal from the DSI block. |
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- power-domains: Should be <&mmcc MDSS_GDSC>. |
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- clocks: Phandles to device clocks. |
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- clock-names: the following clocks are required: |
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* "mdp_core" |
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* "iface" |
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* "bus" |
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* "core_mmss" |
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* "byte" |
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* "pixel" |
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* "core" |
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For DSIv2, we need an additional clock: |
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* "src" |
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For DSI6G v2.0 onwards, we need also need the clock: |
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* "byte_intf" |
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- assigned-clocks: Parents of "byte" and "pixel" for the given platform. |
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- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided |
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by a DSI PHY block. See [1] for details on clock bindings. |
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- vdd-supply: phandle to vdd regulator device node |
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- vddio-supply: phandle to vdd-io regulator device node |
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- vdda-supply: phandle to vdda regulator device node |
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- phys: phandle to DSI PHY device node |
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- phy-names: the name of the corresponding PHY device |
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- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2) |
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- ports: Contains 2 DSI controller ports as child nodes. Each port contains |
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an endpoint subnode as defined in [2] and [3]. |
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Optional properties: |
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- panel@0: Node of panel connected to this DSI controller. |
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See files in [4] for each supported panel. |
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- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is |
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driving a panel which needs 2 DSI links. |
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- qcom,master-dsi: Boolean value indicating if the DSI controller is driving |
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the master link of the 2-DSI panel. |
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- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is |
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driving a 2-DSI panel whose 2 links need receive command simultaneously. |
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- pinctrl-names: the pin control state names; should contain "default" |
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- pinctrl-0: the default pinctrl state (active) |
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- pinctrl-n: the "sleep" pinctrl state |
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- ports: contains DSI controller input and output ports as children, each |
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containing one endpoint subnode. |
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DSI Endpoint properties: |
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- remote-endpoint: For port@0, set to phandle of the connected panel/bridge's |
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input endpoint. For port@1, set to the MDP interface output. See [2] for |
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device graph info. |
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- data-lanes: this describes how the physical DSI data lanes are mapped |
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to the logical lanes on the given platform. The value contained in |
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index n describes what physical lane is mapped to the logical lane n |
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(DATAn, where n lies between 0 and 3). The clock lane position is fixed |
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and can't be changed. Hence, they aren't a part of the DT bindings. See |
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[3] for more info on the data-lanes property. |
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For example: |
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data-lanes = <3 0 1 2>; |
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The above mapping describes that the logical data lane DATA0 is mapped to |
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the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2 |
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to phys DATA1 and logic DATA3 to phys DATA2. |
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There are only a limited number of physical to logical mappings possible: |
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<0 1 2 3> |
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<1 2 3 0> |
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<2 3 0 1> |
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<3 0 1 2> |
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<0 3 2 1> |
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<1 0 3 2> |
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<2 1 0 3> |
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<3 2 1 0> |
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DSI PHY: |
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Required properties: |
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- compatible: Could be the following |
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* "qcom,dsi-phy-28nm-hpm" |
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* "qcom,dsi-phy-28nm-lp" |
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* "qcom,dsi-phy-20nm" |
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* "qcom,dsi-phy-28nm-8960" |
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* "qcom,dsi-phy-14nm" |
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* "qcom,dsi-phy-14nm-660" |
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* "qcom,dsi-phy-10nm" |
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* "qcom,dsi-phy-10nm-8998" |
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* "qcom,dsi-phy-7nm" |
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* "qcom,dsi-phy-7nm-8150" |
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- reg: Physical base address and length of the registers of PLL, PHY. Some |
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revisions require the PHY regulator base address, whereas others require the |
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PHY lane base address. See below for each PHY revision. |
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- reg-names: The names of register regions. The following regions are required: |
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For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: |
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* "dsi_pll" |
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* "dsi_phy" |
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* "dsi_phy_regulator" |
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For DSI 14nm, 10nm and 7nm PHYs: |
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* "dsi_pll" |
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* "dsi_phy" |
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* "dsi_phy_lane" |
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- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating |
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2 clocks: A byte clock (index 0), and a pixel clock (index 1). |
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- power-domains: Should be <&mmcc MDSS_GDSC>. |
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- clocks: Phandles to device clocks. See [1] for details on clock bindings. |
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- clock-names: the following clocks are required: |
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* "iface" |
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* "ref" (only required for new DTS files/entries) |
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For 28nm HPM/LP, 28nm 8960 PHYs: |
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- vddio-supply: phandle to vdd-io regulator device node |
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For 20nm PHY: |
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- vddio-supply: phandle to vdd-io regulator device node |
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- vcca-supply: phandle to vcca regulator device node |
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For 14nm PHY: |
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- vcca-supply: phandle to vcca regulator device node |
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For 10nm and 7nm PHY: |
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- vdds-supply: phandle to vdds regulator device node |
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Optional properties: |
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- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY |
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regulator is wanted. |
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- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode |
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panels in microseconds. Driver uses this number to adjust |
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the clock rate according to the expected transfer time. |
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Increasing this value would slow down the mdp processing |
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and can result in slower performance. |
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Decreasing this value can speed up the mdp processing, |
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but this can also impact power consumption. |
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As a rule this time should not be higher than the time |
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that would be expected with the processing at the |
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dsi link rate since anyways this would be the maximum |
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transfer time that could be achieved. |
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If ping pong split is enabled, this time should not be higher |
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than two times the dsi link rate time. |
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If the property is not specified, then the default value is 14000 us. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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[2] Documentation/devicetree/bindings/graph.txt |
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[3] Documentation/devicetree/bindings/media/video-interfaces.txt |
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[4] Documentation/devicetree/bindings/display/panel/ |
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Example: |
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dsi0: dsi@fd922800 { |
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compatible = "qcom,mdss-dsi-ctrl"; |
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qcom,dsi-host-index = <0>; |
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interrupt-parent = <&mdp>; |
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interrupts = <4 0>; |
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reg-names = "dsi_ctrl"; |
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reg = <0xfd922800 0x200>; |
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power-domains = <&mmcc MDSS_GDSC>; |
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clock-names = |
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"bus", |
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"byte", |
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"core", |
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"core_mmss", |
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"iface", |
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"mdp_core", |
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"pixel"; |
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clocks = |
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<&mmcc MDSS_AXI_CLK>, |
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<&mmcc MDSS_BYTE0_CLK>, |
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<&mmcc MDSS_ESC0_CLK>, |
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<&mmcc MMSS_MISC_AHB_CLK>, |
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<&mmcc MDSS_AHB_CLK>, |
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<&mmcc MDSS_MDP_CLK>, |
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<&mmcc MDSS_PCLK0_CLK>; |
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assigned-clocks = |
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<&mmcc BYTE0_CLK_SRC>, |
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<&mmcc PCLK0_CLK_SRC>; |
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assigned-clock-parents = |
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<&dsi_phy0 0>, |
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<&dsi_phy0 1>; |
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vdda-supply = <&pma8084_l2>; |
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vdd-supply = <&pma8084_l22>; |
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vddio-supply = <&pma8084_l12>; |
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phys = <&dsi_phy0>; |
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phy-names ="dsi-phy"; |
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qcom,dual-dsi-mode; |
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qcom,master-dsi; |
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qcom,sync-dual-dsi; |
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qcom,mdss-mdp-transfer-time-us = <12000>; |
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pinctrl-names = "default", "sleep"; |
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pinctrl-0 = <&dsi_active>; |
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pinctrl-1 = <&dsi_suspend>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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dsi0_in: endpoint { |
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remote-endpoint = <&mdp_intf1_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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dsi0_out: endpoint { |
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remote-endpoint = <&panel_in>; |
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data-lanes = <0 1 2 3>; |
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}; |
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}; |
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}; |
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panel: panel@0 { |
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compatible = "sharp,lq101r1sx01"; |
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reg = <0>; |
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link2 = <&secondary>; |
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power-supply = <...>; |
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backlight = <...>; |
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port { |
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panel_in: endpoint { |
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remote-endpoint = <&dsi0_out>; |
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}; |
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}; |
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}; |
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}; |
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dsi_phy0: dsi-phy@fd922a00 { |
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compatible = "qcom,dsi-phy-28nm-hpm"; |
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qcom,dsi-phy-index = <0>; |
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reg-names = |
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"dsi_pll", |
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"dsi_phy", |
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"dsi_phy_regulator"; |
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reg = <0xfd922a00 0xd4>, |
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<0xfd922b00 0x2b0>, |
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<0xfd922d80 0x7b>; |
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clock-names = "iface"; |
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clocks = <&mmcc MDSS_AHB_CLK>; |
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#clock-cells = <1>; |
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vddio-supply = <&pma8084_l12>; |
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qcom,dsi-phy-regulator-ldo-mode; |
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};
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