mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
170 lines
3.8 KiB
170 lines
3.8 KiB
# SPDX-License-Identifier: GPL-2.0 |
|
%YAML 1.2 |
|
--- |
|
$id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml# |
|
$schema: http://devicetree.org/meta-schemas/core.yaml# |
|
|
|
title: Allwinner A10 HDMI Controller Device Tree Bindings |
|
|
|
description: | |
|
The HDMI Encoder supports the HDMI video and audio outputs, and does |
|
CEC. It is one end of the pipeline. |
|
|
|
maintainers: |
|
- Chen-Yu Tsai <[email protected]> |
|
- Maxime Ripard <[email protected]> |
|
|
|
properties: |
|
compatible: |
|
oneOf: |
|
- const: allwinner,sun4i-a10-hdmi |
|
- const: allwinner,sun5i-a10s-hdmi |
|
- const: allwinner,sun6i-a31-hdmi |
|
- items: |
|
- const: allwinner,sun7i-a20-hdmi |
|
- const: allwinner,sun5i-a10s-hdmi |
|
|
|
reg: |
|
maxItems: 1 |
|
|
|
interrupts: |
|
maxItems: 1 |
|
|
|
clocks: |
|
oneOf: |
|
- items: |
|
- description: The HDMI interface clock |
|
- description: The HDMI module clock |
|
- description: The first video PLL |
|
- description: The second video PLL |
|
|
|
- items: |
|
- description: The HDMI interface clock |
|
- description: The HDMI module clock |
|
- description: The HDMI DDC clock |
|
- description: The first video PLL |
|
- description: The second video PLL |
|
|
|
clock-names: |
|
oneOf: |
|
- items: |
|
- const: ahb |
|
- const: mod |
|
- const: pll-0 |
|
- const: pll-1 |
|
|
|
- items: |
|
- const: ahb |
|
- const: mod |
|
- const: ddc |
|
- const: pll-0 |
|
- const: pll-1 |
|
|
|
resets: |
|
maxItems: 1 |
|
|
|
dmas: |
|
items: |
|
- description: DDC Transmission DMA Channel |
|
- description: DDC Reception DMA Channel |
|
- description: Audio Transmission DMA Channel |
|
|
|
dma-names: |
|
items: |
|
- const: ddc-tx |
|
- const: ddc-rx |
|
- const: audio-tx |
|
|
|
ports: |
|
$ref: /schemas/graph.yaml#/properties/ports |
|
|
|
properties: |
|
port@0: |
|
$ref: /schemas/graph.yaml#/properties/port |
|
description: | |
|
Input endpoints of the controller. |
|
|
|
port@1: |
|
$ref: /schemas/graph.yaml#/properties/port |
|
description: | |
|
Output endpoints of the controller. Usually an HDMI |
|
connector. |
|
|
|
required: |
|
- port@0 |
|
- port@1 |
|
|
|
required: |
|
- compatible |
|
- reg |
|
- interrupts |
|
- clocks |
|
- clock-names |
|
- dmas |
|
- dma-names |
|
|
|
if: |
|
properties: |
|
compatible: |
|
contains: |
|
const: allwinner,sun6i-a31-hdmi |
|
|
|
then: |
|
properties: |
|
clocks: |
|
minItems: 5 |
|
|
|
clock-names: |
|
minItems: 5 |
|
|
|
required: |
|
- resets |
|
|
|
additionalProperties: false |
|
|
|
examples: |
|
- | |
|
#include <dt-bindings/clock/sun4i-a10-ccu.h> |
|
#include <dt-bindings/dma/sun4i-a10.h> |
|
#include <dt-bindings/reset/sun4i-a10-ccu.h> |
|
|
|
hdmi: hdmi@1c16000 { |
|
compatible = "allwinner,sun4i-a10-hdmi"; |
|
reg = <0x01c16000 0x1000>; |
|
interrupts = <58>; |
|
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>, |
|
<&ccu CLK_PLL_VIDEO0_2X>, |
|
<&ccu CLK_PLL_VIDEO1_2X>; |
|
clock-names = "ahb", "mod", "pll-0", "pll-1"; |
|
dmas = <&dma SUN4I_DMA_NORMAL 16>, |
|
<&dma SUN4I_DMA_NORMAL 16>, |
|
<&dma SUN4I_DMA_DEDICATED 24>; |
|
dma-names = "ddc-tx", "ddc-rx", "audio-tx"; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
hdmi_in: port@0 { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
reg = <0>; |
|
|
|
hdmi_in_tcon0: endpoint@0 { |
|
reg = <0>; |
|
remote-endpoint = <&tcon0_out_hdmi>; |
|
}; |
|
|
|
hdmi_in_tcon1: endpoint@1 { |
|
reg = <1>; |
|
remote-endpoint = <&tcon1_out_hdmi>; |
|
}; |
|
}; |
|
|
|
hdmi_out: port@1 { |
|
reg = <1>; |
|
}; |
|
}; |
|
}; |
|
|
|
...
|
|
|