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211 lines
6.5 KiB
211 lines
6.5 KiB
* Clock Block on Freescale QorIQ Platforms |
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Freescale QorIQ chips take primary clocking input from the external |
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SYSCLK signal. The SYSCLK input (frequency) is multiplied using |
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multiple phase locked loops (PLL) to create a variety of frequencies |
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which can then be passed to a variety of internal logic, including |
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cores and peripheral IP blocks. |
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Please refer to the Reference Manual for details. |
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All references to "1.0" and "2.0" refer to the QorIQ chassis version to |
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which the chip complies. |
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Chassis Version Example Chips |
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--------------- ------------- |
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1.0 p4080, p5020, p5040 |
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2.0 t4240, b4860 |
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1. Clock Block Binding |
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Required properties: |
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- compatible: Should contain a chip-specific clock block compatible |
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string and (if applicable) may contain a chassis-version clock |
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compatible string. |
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Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: |
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* "fsl,p2041-clockgen" |
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* "fsl,p3041-clockgen" |
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* "fsl,p4080-clockgen" |
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* "fsl,p5020-clockgen" |
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* "fsl,p5040-clockgen" |
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* "fsl,t1023-clockgen" |
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* "fsl,t1024-clockgen" |
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* "fsl,t1040-clockgen" |
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* "fsl,t1042-clockgen" |
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* "fsl,t2080-clockgen" |
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* "fsl,t2081-clockgen" |
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* "fsl,t4240-clockgen" |
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* "fsl,b4420-clockgen" |
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* "fsl,b4860-clockgen" |
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* "fsl,ls1012a-clockgen" |
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* "fsl,ls1021a-clockgen" |
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* "fsl,ls1028a-clockgen" |
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* "fsl,ls1043a-clockgen" |
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* "fsl,ls1046a-clockgen" |
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* "fsl,ls1088a-clockgen" |
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* "fsl,ls2080a-clockgen" |
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Chassis-version clock strings include: |
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* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks |
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* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks |
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- reg: Describes the address of the device's resources within the |
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address space defined by its parent bus, and resource zero |
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represents the clock register set |
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Optional properties: |
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- ranges: Allows valid translation between child's address space and |
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parent's. Must be present if the device has sub-nodes. |
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- #address-cells: Specifies the number of cells used to represent |
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physical base addresses. Must be present if the device has |
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sub-nodes and set to 1 if present |
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- #size-cells: Specifies the number of cells used to represent |
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the size of an address. Must be present if the device has |
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sub-nodes and set to 1 if present |
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- clock-frequency: Input system clock frequency (SYSCLK) |
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- clocks: If clock-frequency is not specified, sysclk may be provided |
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as an input clock. Either clock-frequency or clocks must be |
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provided. |
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A second input clock, called "coreclk", may be provided if |
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core PLLs are based on a different input clock from the |
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platform PLL. |
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- clock-names: Required if a coreclk is present. Valid names are |
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"sysclk" and "coreclk". |
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2. Clock Provider |
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The clockgen node should act as a clock provider, though in older device |
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trees the children of the clockgen node are the clock providers. |
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When the clockgen node is a clock provider, #clock-cells = <2>. |
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The first cell of the clock specifier is the clock type, and the |
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second cell is the clock index for the specified type. |
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Type# Name Index Cell |
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0 sysclk must be 0 |
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1 cmux index (n in CLKCnCSR) |
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2 hwaccel index (n in CLKCGnHWACSR) |
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3 fman 0 for fm1, 1 for fm2 |
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4 platform pll n=pll/(n+1). For example, when n=1, |
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that means output_freq=PLL_freq/2. |
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5 coreclk must be 0 |
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3. Example |
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clockgen: global-utilities@e1000 { |
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compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; |
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clock-frequency = <133333333>; |
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reg = <0xe1000 0x1000>; |
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#clock-cells = <2>; |
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}; |
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fman@400000 { |
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... |
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clocks = <&clockgen 3 0>; |
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... |
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}; |
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} |
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4. Legacy Child Nodes |
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NOTE: These nodes are deprecated. Kernels should continue to support |
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device trees with these nodes, but new device trees should not use them. |
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Most of the bindings are from the common clock binding[1]. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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Required properties: |
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- compatible : Should include one of the following: |
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* "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0) |
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* "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0) |
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* "fsl,qoriq-core-mux-1.0" for core mux clocks (v1.0) |
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* "fsl,qoriq-core-mux-2.0" for core mux clocks (v2.0) |
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* "fsl,qoriq-sysclk-1.0": for input system clock (v1.0). |
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It takes parent's clock-frequency as its clock. |
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* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0). |
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It takes parent's clock-frequency as its clock. |
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* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0) |
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* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0) |
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- #clock-cells: From common clock binding. The number of cells in a |
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clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0" |
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clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks. |
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For "fsl,qoriq-core-pll-[1,2].0" clocks, the single |
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clock-specifier cell may take the following values: |
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* 0 - equal to the PLL frequency |
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* 1 - equal to the PLL frequency divided by 2 |
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* 2 - equal to the PLL frequency divided by 4 |
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Recommended properties: |
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- clocks: Should be the phandle of input parent clock |
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- clock-names: From common clock binding, indicates the clock name |
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- clock-output-names: From common clock binding, indicates the names of |
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output clocks |
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- reg: Should be the offset and length of clock block base address. |
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The length should be 4. |
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Legacy Example: |
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/ { |
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clockgen: global-utilities@e1000 { |
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compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; |
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ranges = <0x0 0xe1000 0x1000>; |
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clock-frequency = <133333333>; |
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reg = <0xe1000 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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sysclk: sysclk { |
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#clock-cells = <0>; |
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compatible = "fsl,qoriq-sysclk-1.0"; |
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clock-output-names = "sysclk"; |
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}; |
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pll0: pll0@800 { |
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#clock-cells = <1>; |
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reg = <0x800 0x4>; |
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compatible = "fsl,qoriq-core-pll-1.0"; |
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clocks = <&sysclk>; |
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clock-output-names = "pll0", "pll0-div2"; |
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}; |
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pll1: pll1@820 { |
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#clock-cells = <1>; |
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reg = <0x820 0x4>; |
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compatible = "fsl,qoriq-core-pll-1.0"; |
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clocks = <&sysclk>; |
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clock-output-names = "pll1", "pll1-div2"; |
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}; |
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mux0: mux0@0 { |
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#clock-cells = <0>; |
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reg = <0x0 0x4>; |
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compatible = "fsl,qoriq-core-mux-1.0"; |
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; |
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
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clock-output-names = "cmux0"; |
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}; |
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mux1: mux1@20 { |
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#clock-cells = <0>; |
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reg = <0x20 0x4>; |
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compatible = "fsl,qoriq-core-mux-1.0"; |
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clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; |
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clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
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clock-output-names = "cmux1"; |
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}; |
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platform-pll: platform-pll@c00 { |
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#clock-cells = <1>; |
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reg = <0xc00 0x4>; |
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compatible = "fsl,qoriq-platform-pll-1.0"; |
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clocks = <&sysclk>; |
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clock-output-names = "platform-pll", "platform-pll-div2"; |
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}; |
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}; |
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}; |
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Example for legacy clock consumer: |
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/ { |
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cpu0: PowerPC,e5500@0 { |
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... |
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clocks = <&mux0>; |
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... |
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}; |
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};
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