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76 lines
1.7 KiB
76 lines
1.7 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/qcom,gpucc-sdm660.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Qualcomm Graphics Clock & Reset Controller Binding for SDM630 and SDM660 |
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maintainers: |
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- AngeloGioacchino Del Regno <[email protected]> |
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description: | |
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Qualcomm graphics clock control module which supports the clocks, resets and |
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power domains on SDM630 and SDM660. |
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See also dt-bindings/clock/qcom,gpucc-sdm660.h. |
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properties: |
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compatible: |
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enum: |
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- qcom,gpucc-sdm630 |
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- qcom,gpucc-sdm660 |
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clocks: |
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items: |
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- description: Board XO source |
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- description: GPLL0 main gpu branch |
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- description: GPLL0 divider gpu branch |
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clock-names: |
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items: |
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- const: xo |
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- const: gcc_gpu_gpll0_clk |
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- const: gcc_gpu_gpll0_div_clk |
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'#clock-cells': |
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const: 1 |
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'#reset-cells': |
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const: 1 |
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'#power-domain-cells': |
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const: 1 |
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reg: |
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maxItems: 1 |
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required: |
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- compatible |
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- reg |
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- clocks |
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- clock-names |
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- '#clock-cells' |
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- '#reset-cells' |
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- '#power-domain-cells' |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/qcom,gcc-sdm660.h> |
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#include <dt-bindings/clock/qcom,rpmcc.h> |
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clock-controller@5065000 { |
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compatible = "qcom,gpucc-sdm660"; |
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reg = <0x05065000 0x9038>; |
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, |
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<&gcc GCC_GPU_GPLL0_CLK>, |
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<&gcc GCC_GPU_GPLL0_DIV_CLK>; |
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clock-names = "xo", "gcc_gpu_gpll0_clk", |
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"gcc_gpu_gpll0_div_clk"; |
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#clock-cells = <1>; |
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#power-domain-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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...
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