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92 lines
2.4 KiB
92 lines
2.4 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/qcom,gcc-sc7280.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Qualcomm Global Clock & Reset Controller Binding for SC7280 |
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maintainers: |
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- Taniya Das <[email protected]> |
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description: | |
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Qualcomm global clock control module which supports the clocks, resets and |
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power domains on SC7280. |
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See also: |
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- dt-bindings/clock/qcom,gcc-sc7280.h |
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properties: |
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compatible: |
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const: qcom,gcc-sc7280 |
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clocks: |
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items: |
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- description: Board XO source |
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- description: Board active XO source |
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- description: Sleep clock source |
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- description: PCIE-0 pipe clock source |
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- description: PCIE-1 pipe clock source |
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- description: USF phy rx symbol 0 clock source |
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- description: USF phy rx symbol 1 clock source |
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- description: USF phy tx symbol 0 clock source |
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- description: USB30 phy wrapper pipe clock source |
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clock-names: |
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items: |
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- const: bi_tcxo |
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- const: bi_tcxo_ao |
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- const: sleep_clk |
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- const: pcie_0_pipe_clk |
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- const: pcie_1_pipe_clk |
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- const: ufs_phy_rx_symbol_0_clk |
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- const: ufs_phy_rx_symbol_1_clk |
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- const: ufs_phy_tx_symbol_0_clk |
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- const: usb3_phy_wrapper_gcc_usb30_pipe_clk |
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'#clock-cells': |
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const: 1 |
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'#reset-cells': |
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const: 1 |
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'#power-domain-cells': |
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const: 1 |
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reg: |
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maxItems: 1 |
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required: |
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- compatible |
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- clocks |
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- clock-names |
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- reg |
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- '#clock-cells' |
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- '#reset-cells' |
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- '#power-domain-cells' |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/qcom,rpmh.h> |
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clock-controller@100000 { |
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compatible = "qcom,gcc-sc7280"; |
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reg = <0x00100000 0x1f0000>; |
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clocks = <&rpmhcc RPMH_CXO_CLK>, |
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<&rpmhcc RPMH_CXO_CLK_A>, |
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<&sleep_clk>, |
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<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, |
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<&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, |
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<&ufs_phy_tx_symbol_0_clk>, |
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>; |
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clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "pcie_0_pipe_clk", |
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"pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk", |
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"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk", |
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"usb3_phy_wrapper_gcc_usb30_pipe_clk"; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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#power-domain-cells = <1>; |
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}; |
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...
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