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33 lines
869 B
33 lines
869 B
Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller |
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The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB. |
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Required Properties: |
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- compatible: has to be "qca,<soctype>-pll" and one of the following |
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fallbacks: |
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- "qca,ar7100-pll" |
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- "qca,ar7240-pll" |
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- "qca,ar9130-pll" |
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- "qca,ar9330-pll" |
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- "qca,ar9340-pll" |
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- "qca,qca9550-pll" |
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- reg: Base address and size of the controllers memory area |
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- clock-names: Name of the input clock, has to be "ref" |
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- clocks: phandle of the external reference clock |
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- #clock-cells: has to be one |
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Optional properties: |
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- clock-output-names: should be "cpu", "ddr", "ahb" |
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Example: |
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pll-controller@18050000 { |
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compatible = "qca,ar9132-pll", "qca,ar9130-pll"; |
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reg = <0x18050000 0x20>; |
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clock-names = "ref"; |
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clocks = <&extosc>; |
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#clock-cells = <1>; |
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clock-output-names = "cpu", "ddr", "ahb"; |
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};
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