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63 lines
1.5 KiB
63 lines
1.5 KiB
NVIDIA Tegra30 Clock And Reset Controller |
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This binding uses the common clock binding: |
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Documentation/devicetree/bindings/clock/clock-bindings.txt |
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The CAR (Clock And Reset) Controller on Tegra is the HW module responsible |
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for muxing and gating Tegra's clocks, and setting their rates. |
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Required properties : |
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- compatible : Should be "nvidia,tegra30-car" |
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- reg : Should contain CAR registers location and length |
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- clocks : Should contain phandle and clock specifiers for two clocks: |
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the 32 KHz "32k_in", and the board-specific oscillator "osc". |
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- #clock-cells : Should be 1. |
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In clock consumers, this cell represents the clock ID exposed by the |
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CAR. The assignments may be found in header file |
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<dt-bindings/clock/tegra30-car.h>. |
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- #reset-cells : Should be 1. |
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In clock consumers, this cell represents the bit number in the CAR's |
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array of CLK_RST_CONTROLLER_RST_DEVICES_* registers. |
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Example SoC include file: |
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/ { |
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tegra_car: clock { |
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compatible = "nvidia,tegra30-car"; |
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reg = <0x60006000 0x1000>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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}; |
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usb@c5004000 { |
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clocks = <&tegra_car TEGRA30_CLK_USB2>; |
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}; |
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}; |
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Example board file: |
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/ { |
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clocks { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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osc: clock@0 { |
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compatible = "fixed-clock"; |
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reg = <0>; |
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#clock-cells = <0>; |
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clock-frequency = <12000000>; |
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}; |
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clk_32k: clock@1 { |
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compatible = "fixed-clock"; |
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reg = <1>; |
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#clock-cells = <0>; |
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clock-frequency = <32768>; |
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}; |
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}; |
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&tegra_car { |
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clocks = <&clk_32k> <&osc>; |
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}; |
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};
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