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84 lines
2.6 KiB
84 lines
2.6 KiB
Status: Unstable - ABI compatibility may be broken in the future |
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Binding for keystone PLLs. The main PLL IP typically has a multiplier, |
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a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL |
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and PAPLL are controlled by the memory mapped register where as the Main |
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PLL is controlled by a PLL controller registers along with memory mapped |
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registers. |
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This binding uses the common clock binding[1]. |
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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Required properties: |
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- #clock-cells : from common clock binding; shall be set to 0. |
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- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" |
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- clocks : parent clock phandle |
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- reg - pll control0 and pll multipler registers |
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- reg-names : control, multiplier and post-divider. The multiplier and |
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post-divider registers are applicable only for main pll clock |
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- fixed-postdiv : fixed post divider value. If absent, use clkod register bits |
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for postdiv |
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Example: |
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mainpllclk: mainpllclk@2310110 { |
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#clock-cells = <0>; |
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compatible = "ti,keystone,main-pll-clock"; |
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clocks = <&refclksys>; |
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reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; |
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reg-names = "control", "multiplier", "post-divider"; |
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fixed-postdiv = <2>; |
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}; |
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papllclk: papllclk@2620358 { |
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#clock-cells = <0>; |
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compatible = "ti,keystone,pll-clock"; |
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clocks = <&refclkpass>; |
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clock-output-names = "pa-pll-clk"; |
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reg = <0x02620358 4>; |
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reg-names = "control"; |
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}; |
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Required properties: |
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- #clock-cells : from common clock binding; shall be set to 0. |
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- compatible : shall be "ti,keystone,pll-mux-clock" |
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- clocks : link phandles of parent clocks |
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- reg - pll mux register |
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- bit-shift : number of bits to shift the bit-mask |
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- bit-mask : arbitrary bitmask for programming the mux |
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Optional properties: |
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- clock-output-names : From common clock binding. |
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Example: |
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mainmuxclk: mainmuxclk@2310108 { |
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#clock-cells = <0>; |
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compatible = "ti,keystone,pll-mux-clock"; |
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clocks = <&mainpllclk>, <&refclkmain>; |
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reg = <0x02310108 4>; |
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bit-shift = <23>; |
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bit-mask = <1>; |
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clock-output-names = "mainmuxclk"; |
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}; |
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Required properties: |
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- #clock-cells : from common clock binding; shall be set to 0. |
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- compatible : shall be "ti,keystone,pll-divider-clock" |
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- clocks : parent clock phandle |
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- reg - pll mux register |
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- bit-shift : number of bits to shift the bit-mask |
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- bit-mask : arbitrary bitmask for programming the divider |
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Optional properties: |
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- clock-output-names : From common clock binding. |
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Example: |
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gemtraceclk: gemtraceclk@2310120 { |
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#clock-cells = <0>; |
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compatible = "ti,keystone,pll-divider-clock"; |
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clocks = <&mainmuxclk>; |
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reg = <0x02310120 4>; |
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bit-shift = <0>; |
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bit-mask = <8>; |
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clock-output-names = "gemtraceclk"; |
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};
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