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108 lines
2.6 KiB
108 lines
2.6 KiB
* Samsung Exynos7 Clock Controller |
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Exynos7 clock controller has various blocks which are instantiated |
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independently from the device-tree. These clock controllers |
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generate and supply clocks to various hardware blocks within |
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the SoC. |
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Each clock is assigned an identifier and client nodes can use |
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this identifier to specify the clock which they consume. All |
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available clocks are defined as preprocessor macros in |
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dt-bindings/clock/exynos7-clk.h header and can be used in |
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device tree sources. |
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External clocks: |
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There are several clocks that are generated outside the SoC. It |
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is expected that they are defined using standard clock bindings |
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with following clock-output-names: |
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- "fin_pll" - PLL input clock from XXTI |
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Required Properties for Clock Controller: |
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- compatible: clock controllers will use one of the following |
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compatible strings to indicate the clock controller |
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functionality. |
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- "samsung,exynos7-clock-topc" |
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- "samsung,exynos7-clock-top0" |
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- "samsung,exynos7-clock-top1" |
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- "samsung,exynos7-clock-ccore" |
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- "samsung,exynos7-clock-peric0" |
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- "samsung,exynos7-clock-peric1" |
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- "samsung,exynos7-clock-peris" |
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- "samsung,exynos7-clock-fsys0" |
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- "samsung,exynos7-clock-fsys1" |
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- "samsung,exynos7-clock-mscl" |
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- "samsung,exynos7-clock-aud" |
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- reg: physical base address of the controller and the length of |
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memory mapped region. |
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- #clock-cells: should be 1. |
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- clocks: list of clock identifiers which are fed as the input to |
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the given clock controller. Please refer the next section to |
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find the input clocks for a given controller. |
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- clock-names: list of names of clocks which are fed as the input |
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to the given clock controller. |
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Input clocks for top0 clock controller: |
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- fin_pll |
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- dout_sclk_bus0_pll |
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- dout_sclk_bus1_pll |
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- dout_sclk_cc_pll |
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- dout_sclk_mfc_pll |
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- dout_sclk_aud_pll |
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Input clocks for top1 clock controller: |
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- fin_pll |
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- dout_sclk_bus0_pll |
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- dout_sclk_bus1_pll |
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- dout_sclk_cc_pll |
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- dout_sclk_mfc_pll |
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Input clocks for ccore clock controller: |
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- fin_pll |
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- dout_aclk_ccore_133 |
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Input clocks for peric0 clock controller: |
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- fin_pll |
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- dout_aclk_peric0_66 |
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- sclk_uart0 |
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Input clocks for peric1 clock controller: |
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- fin_pll |
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- dout_aclk_peric1_66 |
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- sclk_uart1 |
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- sclk_uart2 |
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- sclk_uart3 |
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- sclk_spi0 |
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- sclk_spi1 |
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- sclk_spi2 |
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- sclk_spi3 |
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- sclk_spi4 |
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- sclk_i2s1 |
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- sclk_pcm1 |
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- sclk_spdif |
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Input clocks for peris clock controller: |
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- fin_pll |
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- dout_aclk_peris_66 |
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Input clocks for fsys0 clock controller: |
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- fin_pll |
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- dout_aclk_fsys0_200 |
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- dout_sclk_mmc2 |
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Input clocks for fsys1 clock controller: |
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- fin_pll |
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- dout_aclk_fsys1_200 |
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- dout_sclk_mmc0 |
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- dout_sclk_mmc1 |
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Input clocks for aud clock controller: |
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- fin_pll |
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- fout_aud_pll
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