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190 lines
5.5 KiB
190 lines
5.5 KiB
* Samsung Exynos5260 Clock Controller |
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Exynos5260 has 13 clock controllers which are instantiated |
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independently from the device-tree. These clock controllers |
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generate and supply clocks to various hardware blocks within |
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the SoC. |
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Each clock is assigned an identifier and client nodes can use |
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this identifier to specify the clock which they consume. All |
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available clocks are defined as preprocessor macros in |
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dt-bindings/clock/exynos5260-clk.h header and can be used in |
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device tree sources. |
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External clocks: |
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There are several clocks that are generated outside the SoC. It |
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is expected that they are defined using standard clock bindings |
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with following clock-output-names: |
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- "fin_pll" - PLL input clock from XXTI |
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- "xrtcxti" - input clock from XRTCXTI |
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- "ioclk_pcm_extclk" - pcm external operation clock |
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- "ioclk_spdif_extclk" - spdif external operation clock |
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- "ioclk_i2s_cdclk" - i2s0 codec clock |
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Phy clocks: |
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There are several clocks which are generated by specific PHYs. |
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These clocks are fed into the clock controller and then routed to |
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the hardware blocks. These clocks are defined as fixed clocks in the |
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driver with following names: |
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- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3 |
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- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2 |
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- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1 |
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- "phyclk_dptx_phy_ch0_txd_clk" - dp phy clock for channel 0 |
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- "phyclk_hdmi_phy_tmds_clko" - hdmi phy tmds clock |
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- "phyclk_hdmi_phy_pixel_clko" - hdmi phy pixel clock |
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- "phyclk_hdmi_link_o_tmds_clkhi" - hdmi phy for hdmi link |
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- "phyclk_dptx_phy_o_ref_clk_24m" - dp phy reference clock |
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- "phyclk_dptx_phy_clk_div2" |
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- "phyclk_mipi_dphy_4l_m_rxclkesc0" |
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- "phyclk_usbhost20_phy_phyclock" - usb 2.0 phy clock |
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- "phyclk_usbhost20_phy_freeclk" |
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- "phyclk_usbhost20_phy_clk48mohci" |
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- "phyclk_usbdrd30_udrd30_pipe_pclk" |
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- "phyclk_usbdrd30_udrd30_phyclock" - usb 3.0 phy clock |
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Required Properties for Clock Controller: |
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- compatible: should be one of the following. |
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1) "samsung,exynos5260-clock-top" |
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2) "samsung,exynos5260-clock-peri" |
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3) "samsung,exynos5260-clock-egl" |
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4) "samsung,exynos5260-clock-kfc" |
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5) "samsung,exynos5260-clock-g2d" |
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6) "samsung,exynos5260-clock-mif" |
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7) "samsung,exynos5260-clock-mfc" |
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8) "samsung,exynos5260-clock-g3d" |
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9) "samsung,exynos5260-clock-fsys" |
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10) "samsung,exynos5260-clock-aud" |
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11) "samsung,exynos5260-clock-isp" |
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12) "samsung,exynos5260-clock-gscl" |
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13) "samsung,exynos5260-clock-disp" |
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- reg: physical base address of the controller and the length of |
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memory mapped region. |
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- #clock-cells: should be 1. |
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- clocks: list of clock identifiers which are fed as the input to |
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the given clock controller. Please refer the next section to find |
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the input clocks for a given controller. |
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- clock-names: list of names of clocks which are fed as the input |
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to the given clock controller. |
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Input clocks for top clock controller: |
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- fin_pll |
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- dout_mem_pll |
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- dout_bus_pll |
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- dout_media_pll |
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Input clocks for peri clock controller: |
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- fin_pll |
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- ioclk_pcm_extclk |
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- ioclk_i2s_cdclk |
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- ioclk_spdif_extclk |
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- phyclk_hdmi_phy_ref_cko |
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- dout_aclk_peri_66 |
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- dout_sclk_peri_uart0 |
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- dout_sclk_peri_uart1 |
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- dout_sclk_peri_uart2 |
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- dout_sclk_peri_spi0_b |
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- dout_sclk_peri_spi1_b |
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- dout_sclk_peri_spi2_b |
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- dout_aclk_peri_aud |
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- dout_sclk_peri_spi0_b |
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Input clocks for egl clock controller: |
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- fin_pll |
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- dout_bus_pll |
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Input clocks for kfc clock controller: |
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- fin_pll |
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- dout_media_pll |
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Input clocks for g2d clock controller: |
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- fin_pll |
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- dout_aclk_g2d_333 |
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Input clocks for mif clock controller: |
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- fin_pll |
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Input clocks for mfc clock controller: |
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- fin_pll |
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- dout_aclk_mfc_333 |
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Input clocks for g3d clock controller: |
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- fin_pll |
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Input clocks for fsys clock controller: |
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- fin_pll |
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- phyclk_usbhost20_phy_phyclock |
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- phyclk_usbhost20_phy_freeclk |
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- phyclk_usbhost20_phy_clk48mohci |
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- phyclk_usbdrd30_udrd30_pipe_pclk |
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- phyclk_usbdrd30_udrd30_phyclock |
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- dout_aclk_fsys_200 |
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Input clocks for aud clock controller: |
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- fin_pll |
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- fout_aud_pll |
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- ioclk_i2s_cdclk |
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- ioclk_pcm_extclk |
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Input clocks for isp clock controller: |
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- fin_pll |
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- dout_aclk_isp1_266 |
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- dout_aclk_isp1_400 |
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- mout_aclk_isp1_266 |
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Input clocks for gscl clock controller: |
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- fin_pll |
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- dout_aclk_gscl_400 |
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- dout_aclk_gscl_333 |
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Input clocks for disp clock controller: |
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- fin_pll |
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- phyclk_dptx_phy_ch3_txd_clk |
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- phyclk_dptx_phy_ch2_txd_clk |
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- phyclk_dptx_phy_ch1_txd_clk |
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- phyclk_dptx_phy_ch0_txd_clk |
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- phyclk_hdmi_phy_tmds_clko |
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- phyclk_hdmi_phy_ref_clko |
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- phyclk_hdmi_phy_pixel_clko |
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- phyclk_hdmi_link_o_tmds_clkhi |
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- phyclk_mipi_dphy_4l_m_txbyte_clkhs |
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- phyclk_dptx_phy_o_ref_clk_24m |
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- phyclk_dptx_phy_clk_div2 |
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- phyclk_mipi_dphy_4l_m_rxclkesc0 |
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- phyclk_hdmi_phy_ref_cko |
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- ioclk_spdif_extclk |
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- dout_aclk_peri_aud |
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- dout_aclk_disp_222 |
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- dout_sclk_disp_pixel |
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- dout_aclk_disp_333 |
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Example 1: An example of a clock controller node is listed below. |
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clock_mfc: clock-controller@11090000 { |
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compatible = "samsung,exynos5260-clock-mfc"; |
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clock = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_MFC_333>; |
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clock-names = "fin_pll", "dout_aclk_mfc_333"; |
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reg = <0x11090000 0x10000>; |
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#clock-cells = <1>; |
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}; |
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Example 2: UART controller node that consumes the clock generated by the |
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peri clock controller. Refer to the standard clock bindings for |
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information about 'clocks' and 'clock-names' property. |
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serial@12c00000 { |
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compatible = "samsung,exynos4210-uart"; |
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reg = <0x12C00000 0x100>; |
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interrupts = <0 146 0>; |
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clocks = <&clock_peri PERI_PCLK_UART0>, <&clock_peri PERI_SCLK_UART0>; |
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clock-names = "uart", "clk_uart_baud0"; |
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}; |
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