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53 lines
1.0 KiB
53 lines
1.0 KiB
# SPDX-License-Identifier: GPL-2.0 |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Allwinner A10 Peripheral PLL Device Tree Bindings |
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maintainers: |
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- Chen-Yu Tsai <[email protected]> |
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- Maxime Ripard <[email protected]> |
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deprecated: true |
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properties: |
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"#clock-cells": |
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const: 1 |
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description: > |
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The first output is the SATA clock output, the second is the |
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regular PLL output, the third is a PLL output at twice the rate. |
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compatible: |
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const: allwinner,sun4i-a10-pll6-clk |
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reg: |
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maxItems: 1 |
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clocks: |
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maxItems: 1 |
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clock-output-names: |
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maxItems: 3 |
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required: |
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- "#clock-cells" |
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- compatible |
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- reg |
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- clocks |
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- clock-output-names |
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additionalProperties: false |
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examples: |
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- | |
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clk@1c20028 { |
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#clock-cells = <1>; |
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compatible = "allwinner,sun4i-a10-pll6-clk"; |
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reg = <0x01c20028 0x4>; |
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clocks = <&osc24M>; |
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clock-output-names = "pll6_sata", "pll6_other", "pll6"; |
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}; |
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...
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