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322 lines
8.6 KiB
322 lines
8.6 KiB
/* |
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* adc-mkl27z.c - ADC driver for MKL27Z |
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* In this ADC driver, there are NeuG specific parts. |
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* It only records lower 8-bit of 16-bit data. |
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* You need to modify to use this as generic ADC driver. |
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* |
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* Copyright (C) 2016 Flying Stone Technology |
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* Author: NIIBE Yutaka <[email protected]> |
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* |
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* This file is a part of Chopstx, a thread library for embedded. |
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* |
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* Chopstx is free software: you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by |
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* the Free Software Foundation, either version 3 of the License, or |
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* (at your option) any later version. |
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* |
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* Chopstx is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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* General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>. |
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* |
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* As additional permission under GNU GPL version 3 section 7, you may |
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* distribute non-source form of the Program without the copy of the |
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* GNU GPL normally required by section 4, provided you inform the |
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* receipents of GNU GPL by a written offer. |
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* |
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*/ |
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#include <stdint.h> |
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#include <stdlib.h> |
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#include <chopstx.h> |
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#include <mcu/mkl27z.h> |
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struct DMAMUX { |
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volatile uint32_t CHCFG0; |
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volatile uint32_t CHCFG1; |
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volatile uint32_t CHCFG2; |
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volatile uint32_t CHCFG3; |
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}; |
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static struct DMAMUX *const DMAMUX = (struct DMAMUX *)0x40021000; |
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#define INTR_REQ_DMA0 0 |
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struct DMA { |
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volatile uint32_t SAR; |
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volatile uint32_t DAR; |
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volatile uint32_t DSR_BCR; |
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volatile uint32_t DCR; |
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}; |
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static struct DMA *const DMA0 = (struct DMA *)0x40008100; |
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static struct DMA *const DMA1 = (struct DMA *)0x40008110; |
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/* We don't use ADC interrupt. Just for reference. */ |
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#define INTR_REQ_ADC 15 |
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struct ADC { |
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volatile uint32_t SC1[2];/* Status and Control Registers 1 */ |
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volatile uint32_t CFG1; /* Configuration Register 1 */ |
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volatile uint32_t CFG2; /* Configuration Register 2 */ |
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volatile uint32_t R[2]; /* Data Result Register */ |
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/* Compare Value Registers 1, 2 */ |
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volatile uint32_t CV1; |
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volatile uint32_t CV2; |
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volatile uint32_t SC2; /* Status and Control Register 2 */ |
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volatile uint32_t SC3; /* Status and Control Register 3 */ |
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volatile uint32_t OFS; /* Offset Correction Register */ |
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volatile uint32_t PG; /* Plus-Side Gain Register */ |
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volatile uint32_t MG; /* Minus-Side Gain Register */ |
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/* Plus-Side General Calibration Value Registers */ |
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volatile uint32_t CLPD; |
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volatile uint32_t CLPS; |
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volatile uint32_t CLP4; |
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volatile uint32_t CLP3; |
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volatile uint32_t CLP2; |
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volatile uint32_t CLP1; |
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volatile uint32_t CLP0; |
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uint32_t rsvd0; |
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/* Minus-Side General Calibration Value Registers */ |
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volatile uint32_t CLMD; |
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volatile uint32_t CLMS; |
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volatile uint32_t CLM4; |
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volatile uint32_t CLM3; |
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volatile uint32_t CLM2; |
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volatile uint32_t CLM1; |
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volatile uint32_t CLM0; |
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}; |
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static struct ADC *const ADC0 = (struct ADC *)0x4003B000; |
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/* SC1 */ |
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#define ADC_SC1_DIFF (1 << 5) |
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#define ADC_SC1_AIEN (1 << 6) |
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#define ADC_SC1_COCO (1 << 7) |
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#define ADC_SC1_TEMPSENSOR 26 |
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#define ADC_SC1_BANDGAP 27 |
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#define ADC_SC1_ADCSTOP 31 |
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/* CFG1 */ |
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#define ADC_CLOCK_SOURCE_ASYNCH (3 << 0) |
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#define ADC_MODE_16BIT (3 << 2) |
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#define ADC_ADLSMP_SHORT (0 << 4) |
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#define ADC_ADLSMP_LONG (1 << 4) |
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#define ADC_ADIV_1 (0 << 5) |
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#define ADC_ADIV_8 (3 << 5) |
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#define ADC_ADLPC_NORMAL (0 << 7) |
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#define ADC_ADLPC_LOWPOWER (1 << 7) |
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/**/ |
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#define ADC_CLOCK_SOURCE ADC_CLOCK_SOURCE_ASYNCH |
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#define ADC_MODE ADC_MODE_16BIT |
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#define ADC_ADLSMP ADC_ADLSMP_SHORT |
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#define ADC_ADIV ADC_ADIV_1 |
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#define ADC_ADLPC ADC_ADLPC_LOWPOWER |
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/* CFG2 */ |
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#define ADC_ADLSTS_DEFAULT 0 /* 24 cycles if CFG1.ADLSMP=1, 4 if not. */ |
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#define ADC_ADHSC_NORMAL (0 << 2) |
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#define ADC_ADHSC_HIGHSPEED (1 << 2) |
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#define ADC_ADACK_DISABLE (0 << 3) |
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#define ADC_ADACK_ENABLE (1 << 3) |
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#define ADC_MUXSEL_A (0 << 4) |
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#define ADC_MUXSEL_B (1 << 4) |
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/**/ |
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#define ADC_ADLSTS ADC_ADLSTS_DEFAULT |
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#define ADC_ADHSC ADC_ADHSC_NORMAL |
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#define ADC_ADACKEN ADC_ADACK_ENABLE |
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#define ADC_MUXSEL ADC_MUXSEL_A |
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/* SC2 */ |
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#define ADC_SC2_REFSEL_DEFAULT 1 /* Internal Voltage Reference??? */ |
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#define ADC_SC2_DMAEN (1 << 2) |
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#define ADC_SC2_ACREN (1 << 3) |
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#define ADC_SC2_ACFGT (1 << 4) |
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#define ADC_SC2_ACFE (1 << 5) |
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#define ADC_SC2_ADTRG (1 << 6) /* For hardware trigger */ |
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/* SC3 */ |
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#define ADC_SC3_AVGS11 0x03 |
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#define ADC_SC3_AVGE (1 << 2) |
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#define ADC_SC3_ADCO (1 << 3) |
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#define ADC_SC3_CALF (1 << 6) |
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#define ADC_SC3_CAL (1 << 7) |
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#define ADC_DMA_SLOT_NUM 40 |
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/* |
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* Buffer to save ADC data. |
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*/ |
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uint32_t adc_buf[64]; |
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static const uint32_t adc0_sc1_setting = ADC_SC1_TEMPSENSOR; |
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static chopstx_intr_t adc_intr; |
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struct adc_internal { |
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uint32_t buf[64]; |
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uint8_t *p; |
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int phase : 8; |
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int count : 8; |
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}; |
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struct adc_internal adc; |
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/* |
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* Initialize ADC module, do calibration. |
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* |
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* This is called by MAIN, only once, hopefully before creating any |
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* other threads (to be accurate). |
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* |
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* We configure ADC0 to kick DMA0, configure DMA0 to kick DMA1. |
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* DMA0 records output of ADC0 to the ADC.BUF. |
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* DMA1 kicks ADC0 again to get another value. |
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* |
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* ADC0 --[finish conversion]--> DMA0 --[Link channel 1]--> DMA1 |
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*/ |
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int |
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adc_init (void) |
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{ |
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uint32_t v; |
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/* Enable ADC0 and DMAMUX clock. */ |
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SIM->SCGC6 |= (1 << 27) | (1 << 1); |
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/* Enable DMA clock. */ |
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SIM->SCGC7 |= (1 << 8); |
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/* ADC0 setting for calibration. */ |
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ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC; |
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ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL; |
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ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT; |
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ADC0->SC3 = ADC_SC3_CAL | ADC_SC3_CALF | ADC_SC3_AVGE | ADC_SC3_AVGS11; |
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/* Wait ADC completion */ |
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while ((ADC0->SC1[0] & ADC_SC1_COCO) == 0) |
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if ((ADC0->SC3 & ADC_SC3_CALF) != 0) |
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/* Calibration failure */ |
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return -1; |
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if ((ADC0->SC3 & ADC_SC3_CALF) != 0) |
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/* Calibration failure */ |
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return -1; |
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/* Configure PG by the calibration values. */ |
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v = ADC0->CLP0 + ADC0->CLP1 + ADC0->CLP2 + ADC0->CLP3 + ADC0->CLP4 + ADC0->CLPS; |
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ADC0->PG = 0x8000 | (v >> 1); |
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/* Configure MG by the calibration values. */ |
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v = ADC0->CLM0 + ADC0->CLM1 + ADC0->CLM2 + ADC0->CLM3 + ADC0->CLM4 + ADC0->CLMS; |
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ADC0->MG = 0x8000 | (v >> 1); |
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ADC0->SC1[0] = ADC_SC1_ADCSTOP; |
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/* DMAMUX setting. */ |
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DMAMUX->CHCFG0 = (1 << 7) | ADC_DMA_SLOT_NUM; |
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/* DMA0 initial setting. */ |
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DMA0->SAR = (uint32_t)&ADC0->R[0]; |
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/* DMA1 initial setting. */ |
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DMA1->SAR = (uint32_t)&adc0_sc1_setting; |
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DMA1->DAR = (uint32_t)&ADC0->SC1[0]; |
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chopstx_claim_irq (&adc_intr, INTR_REQ_DMA0); |
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return 0; |
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} |
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/* |
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* Start using ADC. |
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*/ |
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void |
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adc_start (void) |
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{ |
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ADC0->CFG1 = ADC_CLOCK_SOURCE | ADC_MODE | ADC_ADLSMP | ADC_ADIV | ADC_ADLPC; |
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ADC0->CFG2 = ADC_ADLSTS | ADC_ADHSC | ADC_ADACKEN | ADC_MUXSEL; |
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ADC0->SC2 = ADC_SC2_REFSEL_DEFAULT | ADC_SC2_DMAEN; |
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ADC0->SC3 = 0; |
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} |
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/* |
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* Kick getting data for COUNT times. |
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* Data will be saved in ADC_BUF starting at OFFSET. |
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*/ |
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static void |
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adc_start_conversion_internal (int count) |
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{ |
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/* DMA0 setting. */ |
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DMA0->DAR = (uint32_t)&adc.buf[0]; |
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DMA0->DSR_BCR = 4 * count; |
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DMA0->DCR = (1 << 31) | (1 << 30) | (1 << 29) | (0 << 20) | (1 << 19) |
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| (0 << 17) | (1 << 7) | (2 << 4) | (1 << 2); |
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/* Kick DMA1. */ |
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DMA1->DSR_BCR = 4 * count; |
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DMA1->DCR = (1 << 30) | (1 << 29) | (0 << 19) | (0 << 17) | (1 << 16) | (1 << 7); |
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} |
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/* |
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* Kick getting data for COUNT times. |
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* Data will be saved in ADC_BUF starting at OFFSET. |
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*/ |
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void |
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adc_start_conversion (int offset, int count) |
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{ |
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adc.p = (uint8_t *)&adc_buf[offset]; |
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adc.phase = 0; |
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adc.count = count; |
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adc_start_conversion_internal (count); |
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} |
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static void |
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adc_stop_conversion (void) |
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{ |
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ADC0->SC1[0] = ADC_SC1_ADCSTOP; |
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} |
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/* |
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* Stop using ADC. |
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*/ |
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void |
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adc_stop (void) |
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{ |
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SIM->SCGC6 &= ~(1 << 27); |
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} |
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/* |
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* Return 0 on success. |
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* Return 1 on error. |
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*/ |
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int |
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adc_wait_completion (void) |
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{ |
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int i; |
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while (1) |
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{ |
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/* Wait DMA completion */ |
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chopstx_intr_wait (&adc_intr); |
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DMA0->DSR_BCR = (1 << 24); |
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DMA1->DSR_BCR = (1 << 24); |
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adc_stop_conversion (); |
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chopstx_intr_done (&adc_intr); |
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for (i = 0; i < adc.count; i++) |
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*adc.p++ = (uint8_t)adc.buf[i]; |
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if (++adc.phase >= 4) |
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break; |
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adc_start_conversion_internal (adc.count); |
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} |
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return 0; |
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}
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