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678 lines
13 KiB
678 lines
13 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Support for Vector Instructions |
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* |
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* Assembler macros to generate .byte/.word code for particular |
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* vector instructions that are supported by recent binutils (>= 2.26) only. |
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* |
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* Copyright IBM Corp. 2015 |
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* Author(s): Hendrik Brueckner <[email protected]> |
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*/ |
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#ifndef __ASM_S390_VX_INSN_H |
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#define __ASM_S390_VX_INSN_H |
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#ifdef __ASSEMBLY__ |
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/* Macros to generate vector instruction byte code */ |
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/* GR_NUM - Retrieve general-purpose register number |
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* |
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* @opd: Operand to store register number |
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* @r64: String designation register in the format "%rN" |
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*/ |
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.macro GR_NUM opd gr |
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\opd = 255 |
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.ifc \gr,%r0 |
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\opd = 0 |
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.endif |
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.ifc \gr,%r1 |
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\opd = 1 |
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.endif |
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.ifc \gr,%r2 |
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\opd = 2 |
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.endif |
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.ifc \gr,%r3 |
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\opd = 3 |
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.endif |
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.ifc \gr,%r4 |
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\opd = 4 |
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.endif |
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.ifc \gr,%r5 |
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\opd = 5 |
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.endif |
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.ifc \gr,%r6 |
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\opd = 6 |
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.endif |
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.ifc \gr,%r7 |
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\opd = 7 |
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.endif |
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.ifc \gr,%r8 |
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\opd = 8 |
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.endif |
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.ifc \gr,%r9 |
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\opd = 9 |
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.endif |
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.ifc \gr,%r10 |
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\opd = 10 |
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.endif |
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.ifc \gr,%r11 |
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\opd = 11 |
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.endif |
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.ifc \gr,%r12 |
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\opd = 12 |
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.endif |
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.ifc \gr,%r13 |
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\opd = 13 |
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.endif |
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.ifc \gr,%r14 |
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\opd = 14 |
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.endif |
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.ifc \gr,%r15 |
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\opd = 15 |
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.endif |
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.if \opd == 255 |
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\opd = \gr |
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.endif |
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.endm |
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/* VX_NUM - Retrieve vector register number |
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* |
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* @opd: Operand to store register number |
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* @vxr: String designation register in the format "%vN" |
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* |
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* The vector register number is used for as input number to the |
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* instruction and, as well as, to compute the RXB field of the |
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* instruction. |
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*/ |
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.macro VX_NUM opd vxr |
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\opd = 255 |
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.ifc \vxr,%v0 |
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\opd = 0 |
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.endif |
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.ifc \vxr,%v1 |
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\opd = 1 |
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.endif |
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.ifc \vxr,%v2 |
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\opd = 2 |
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.endif |
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.ifc \vxr,%v3 |
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\opd = 3 |
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.endif |
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.ifc \vxr,%v4 |
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\opd = 4 |
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.endif |
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.ifc \vxr,%v5 |
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\opd = 5 |
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.endif |
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.ifc \vxr,%v6 |
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\opd = 6 |
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.endif |
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.ifc \vxr,%v7 |
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\opd = 7 |
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.endif |
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.ifc \vxr,%v8 |
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\opd = 8 |
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.endif |
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.ifc \vxr,%v9 |
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\opd = 9 |
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.endif |
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.ifc \vxr,%v10 |
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\opd = 10 |
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.endif |
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.ifc \vxr,%v11 |
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\opd = 11 |
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.endif |
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.ifc \vxr,%v12 |
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\opd = 12 |
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.endif |
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.ifc \vxr,%v13 |
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\opd = 13 |
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.endif |
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.ifc \vxr,%v14 |
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\opd = 14 |
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.endif |
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.ifc \vxr,%v15 |
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\opd = 15 |
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.endif |
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.ifc \vxr,%v16 |
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\opd = 16 |
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.endif |
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.ifc \vxr,%v17 |
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\opd = 17 |
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.endif |
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.ifc \vxr,%v18 |
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\opd = 18 |
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.endif |
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.ifc \vxr,%v19 |
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\opd = 19 |
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.endif |
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.ifc \vxr,%v20 |
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\opd = 20 |
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.endif |
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.ifc \vxr,%v21 |
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\opd = 21 |
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.endif |
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.ifc \vxr,%v22 |
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\opd = 22 |
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.endif |
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.ifc \vxr,%v23 |
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\opd = 23 |
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.endif |
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.ifc \vxr,%v24 |
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\opd = 24 |
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.endif |
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.ifc \vxr,%v25 |
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\opd = 25 |
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.endif |
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.ifc \vxr,%v26 |
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\opd = 26 |
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.endif |
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.ifc \vxr,%v27 |
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\opd = 27 |
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.endif |
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.ifc \vxr,%v28 |
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\opd = 28 |
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.endif |
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.ifc \vxr,%v29 |
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\opd = 29 |
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.endif |
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.ifc \vxr,%v30 |
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\opd = 30 |
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.endif |
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.ifc \vxr,%v31 |
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\opd = 31 |
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.endif |
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.if \opd == 255 |
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\opd = \vxr |
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.endif |
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.endm |
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/* RXB - Compute most significant bit used vector registers |
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* |
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* @rxb: Operand to store computed RXB value |
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* @v1: First vector register designated operand |
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* @v2: Second vector register designated operand |
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* @v3: Third vector register designated operand |
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* @v4: Fourth vector register designated operand |
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*/ |
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.macro RXB rxb v1 v2=0 v3=0 v4=0 |
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\rxb = 0 |
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.if \v1 & 0x10 |
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\rxb = \rxb | 0x08 |
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.endif |
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.if \v2 & 0x10 |
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\rxb = \rxb | 0x04 |
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.endif |
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.if \v3 & 0x10 |
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\rxb = \rxb | 0x02 |
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.endif |
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.if \v4 & 0x10 |
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\rxb = \rxb | 0x01 |
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.endif |
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.endm |
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/* MRXB - Generate Element Size Control and RXB value |
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* |
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* @m: Element size control |
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* @v1: First vector register designated operand (for RXB) |
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* @v2: Second vector register designated operand (for RXB) |
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* @v3: Third vector register designated operand (for RXB) |
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* @v4: Fourth vector register designated operand (for RXB) |
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*/ |
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.macro MRXB m v1 v2=0 v3=0 v4=0 |
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rxb = 0 |
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RXB rxb, \v1, \v2, \v3, \v4 |
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.byte (\m << 4) | rxb |
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.endm |
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/* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields |
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* |
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* @m: Element size control |
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* @opc: Opcode |
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* @v1: First vector register designated operand (for RXB) |
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* @v2: Second vector register designated operand (for RXB) |
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* @v3: Third vector register designated operand (for RXB) |
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* @v4: Fourth vector register designated operand (for RXB) |
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*/ |
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.macro MRXBOPC m opc v1 v2=0 v3=0 v4=0 |
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MRXB \m, \v1, \v2, \v3, \v4 |
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.byte \opc |
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.endm |
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/* Vector support instructions */ |
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/* VECTOR GENERATE BYTE MASK */ |
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.macro VGBM vr imm2 |
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VX_NUM v1, \vr |
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.word (0xE700 | ((v1&15) << 4)) |
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.word \imm2 |
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MRXBOPC 0, 0x44, v1 |
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.endm |
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.macro VZERO vxr |
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VGBM \vxr, 0 |
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.endm |
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.macro VONE vxr |
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VGBM \vxr, 0xFFFF |
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.endm |
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/* VECTOR LOAD VR ELEMENT FROM GR */ |
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.macro VLVG v, gr, disp, m |
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VX_NUM v1, \v |
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GR_NUM b2, "%r0" |
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GR_NUM r3, \gr |
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.word 0xE700 | ((v1&15) << 4) | r3 |
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.word (b2 << 12) | (\disp) |
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MRXBOPC \m, 0x22, v1 |
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.endm |
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.macro VLVGB v, gr, index, base |
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VLVG \v, \gr, \index, \base, 0 |
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.endm |
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.macro VLVGH v, gr, index |
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VLVG \v, \gr, \index, 1 |
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.endm |
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.macro VLVGF v, gr, index |
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VLVG \v, \gr, \index, 2 |
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.endm |
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.macro VLVGG v, gr, index |
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VLVG \v, \gr, \index, 3 |
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.endm |
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/* VECTOR LOAD REGISTER */ |
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.macro VLR v1, v2 |
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VX_NUM v1, \v1 |
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VX_NUM v2, \v2 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word 0 |
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MRXBOPC 0, 0x56, v1, v2 |
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.endm |
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/* VECTOR LOAD */ |
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.macro VL v, disp, index="%r0", base |
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VX_NUM v1, \v |
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GR_NUM x2, \index |
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GR_NUM b2, \base |
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.word 0xE700 | ((v1&15) << 4) | x2 |
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.word (b2 << 12) | (\disp) |
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MRXBOPC 0, 0x06, v1 |
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.endm |
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/* VECTOR LOAD ELEMENT */ |
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.macro VLEx vr1, disp, index="%r0", base, m3, opc |
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VX_NUM v1, \vr1 |
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GR_NUM x2, \index |
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GR_NUM b2, \base |
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.word 0xE700 | ((v1&15) << 4) | x2 |
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.word (b2 << 12) | (\disp) |
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MRXBOPC \m3, \opc, v1 |
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.endm |
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.macro VLEB vr1, disp, index="%r0", base, m3 |
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VLEx \vr1, \disp, \index, \base, \m3, 0x00 |
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.endm |
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.macro VLEH vr1, disp, index="%r0", base, m3 |
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VLEx \vr1, \disp, \index, \base, \m3, 0x01 |
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.endm |
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.macro VLEF vr1, disp, index="%r0", base, m3 |
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VLEx \vr1, \disp, \index, \base, \m3, 0x03 |
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.endm |
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.macro VLEG vr1, disp, index="%r0", base, m3 |
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VLEx \vr1, \disp, \index, \base, \m3, 0x02 |
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.endm |
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/* VECTOR LOAD ELEMENT IMMEDIATE */ |
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.macro VLEIx vr1, imm2, m3, opc |
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VX_NUM v1, \vr1 |
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.word 0xE700 | ((v1&15) << 4) |
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.word \imm2 |
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MRXBOPC \m3, \opc, v1 |
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.endm |
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.macro VLEIB vr1, imm2, index |
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VLEIx \vr1, \imm2, \index, 0x40 |
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.endm |
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.macro VLEIH vr1, imm2, index |
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VLEIx \vr1, \imm2, \index, 0x41 |
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.endm |
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.macro VLEIF vr1, imm2, index |
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VLEIx \vr1, \imm2, \index, 0x43 |
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.endm |
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.macro VLEIG vr1, imm2, index |
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VLEIx \vr1, \imm2, \index, 0x42 |
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.endm |
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/* VECTOR LOAD GR FROM VR ELEMENT */ |
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.macro VLGV gr, vr, disp, base="%r0", m |
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GR_NUM r1, \gr |
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GR_NUM b2, \base |
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VX_NUM v3, \vr |
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.word 0xE700 | (r1 << 4) | (v3&15) |
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.word (b2 << 12) | (\disp) |
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MRXBOPC \m, 0x21, v3 |
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.endm |
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.macro VLGVB gr, vr, disp, base="%r0" |
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VLGV \gr, \vr, \disp, \base, 0 |
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.endm |
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.macro VLGVH gr, vr, disp, base="%r0" |
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VLGV \gr, \vr, \disp, \base, 1 |
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.endm |
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.macro VLGVF gr, vr, disp, base="%r0" |
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VLGV \gr, \vr, \disp, \base, 2 |
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.endm |
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.macro VLGVG gr, vr, disp, base="%r0" |
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VLGV \gr, \vr, \disp, \base, 3 |
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.endm |
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/* VECTOR LOAD MULTIPLE */ |
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.macro VLM vfrom, vto, disp, base, hint=3 |
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VX_NUM v1, \vfrom |
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VX_NUM v3, \vto |
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GR_NUM b2, \base /* Base register */ |
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.word 0xE700 | ((v1&15) << 4) | (v3&15) |
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.word (b2 << 12) | (\disp) |
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MRXBOPC \hint, 0x36, v1, v3 |
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.endm |
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/* VECTOR STORE */ |
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.macro VST vr1, disp, index="%r0", base |
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VX_NUM v1, \vr1 |
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GR_NUM x2, \index |
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GR_NUM b2, \base /* Base register */ |
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.word 0xE700 | ((v1&15) << 4) | (x2&15) |
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.word (b2 << 12) | (\disp) |
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MRXBOPC 0, 0x0E, v1 |
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.endm |
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/* VECTOR STORE MULTIPLE */ |
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.macro VSTM vfrom, vto, disp, base, hint=3 |
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VX_NUM v1, \vfrom |
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VX_NUM v3, \vto |
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GR_NUM b2, \base /* Base register */ |
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.word 0xE700 | ((v1&15) << 4) | (v3&15) |
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.word (b2 << 12) | (\disp) |
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MRXBOPC \hint, 0x3E, v1, v3 |
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.endm |
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/* VECTOR PERMUTE */ |
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.macro VPERM vr1, vr2, vr3, vr4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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VX_NUM v4, \vr4 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4 |
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.endm |
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/* VECTOR UNPACK LOGICAL LOW */ |
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.macro VUPLL vr1, vr2, m3 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word 0x0000 |
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MRXBOPC \m3, 0xD4, v1, v2 |
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.endm |
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.macro VUPLLB vr1, vr2 |
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VUPLL \vr1, \vr2, 0 |
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.endm |
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.macro VUPLLH vr1, vr2 |
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VUPLL \vr1, \vr2, 1 |
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.endm |
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.macro VUPLLF vr1, vr2 |
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VUPLL \vr1, \vr2, 2 |
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.endm |
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/* VECTOR PERMUTE DOUBLEWORD IMMEDIATE */ |
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.macro VPDI vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0x84, v1, v2, v3 |
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.endm |
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/* VECTOR REPLICATE */ |
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.macro VREP vr1, vr3, imm2, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v3&15) |
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.word \imm2 |
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MRXBOPC \m4, 0x4D, v1, v3 |
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.endm |
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.macro VREPB vr1, vr3, imm2 |
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VREP \vr1, \vr3, \imm2, 0 |
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.endm |
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.macro VREPH vr1, vr3, imm2 |
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VREP \vr1, \vr3, \imm2, 1 |
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.endm |
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.macro VREPF vr1, vr3, imm2 |
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VREP \vr1, \vr3, \imm2, 2 |
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.endm |
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.macro VREPG vr1, vr3, imm2 |
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VREP \vr1, \vr3, \imm2, 3 |
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.endm |
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/* VECTOR MERGE HIGH */ |
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.macro VMRH vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0x61, v1, v2, v3 |
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.endm |
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.macro VMRHB vr1, vr2, vr3 |
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VMRH \vr1, \vr2, \vr3, 0 |
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.endm |
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.macro VMRHH vr1, vr2, vr3 |
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VMRH \vr1, \vr2, \vr3, 1 |
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.endm |
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.macro VMRHF vr1, vr2, vr3 |
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VMRH \vr1, \vr2, \vr3, 2 |
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.endm |
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.macro VMRHG vr1, vr2, vr3 |
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VMRH \vr1, \vr2, \vr3, 3 |
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.endm |
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/* VECTOR MERGE LOW */ |
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.macro VMRL vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0x60, v1, v2, v3 |
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.endm |
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.macro VMRLB vr1, vr2, vr3 |
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VMRL \vr1, \vr2, \vr3, 0 |
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.endm |
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.macro VMRLH vr1, vr2, vr3 |
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VMRL \vr1, \vr2, \vr3, 1 |
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.endm |
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.macro VMRLF vr1, vr2, vr3 |
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VMRL \vr1, \vr2, \vr3, 2 |
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.endm |
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.macro VMRLG vr1, vr2, vr3 |
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VMRL \vr1, \vr2, \vr3, 3 |
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.endm |
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/* Vector integer instructions */ |
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/* VECTOR AND */ |
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.macro VN vr1, vr2, vr3 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC 0, 0x68, v1, v2, v3 |
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.endm |
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/* VECTOR EXCLUSIVE OR */ |
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.macro VX vr1, vr2, vr3 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC 0, 0x6D, v1, v2, v3 |
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.endm |
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/* VECTOR GALOIS FIELD MULTIPLY SUM */ |
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.macro VGFM vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0xB4, v1, v2, v3 |
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.endm |
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.macro VGFMB vr1, vr2, vr3 |
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VGFM \vr1, \vr2, \vr3, 0 |
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.endm |
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.macro VGFMH vr1, vr2, vr3 |
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VGFM \vr1, \vr2, \vr3, 1 |
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.endm |
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.macro VGFMF vr1, vr2, vr3 |
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VGFM \vr1, \vr2, \vr3, 2 |
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.endm |
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.macro VGFMG vr1, vr2, vr3 |
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VGFM \vr1, \vr2, \vr3, 3 |
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.endm |
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/* VECTOR GALOIS FIELD MULTIPLY SUM AND ACCUMULATE */ |
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.macro VGFMA vr1, vr2, vr3, vr4, m5 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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VX_NUM v4, \vr4 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) | (\m5 << 8) |
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MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4 |
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.endm |
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.macro VGFMAB vr1, vr2, vr3, vr4 |
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VGFMA \vr1, \vr2, \vr3, \vr4, 0 |
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.endm |
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.macro VGFMAH vr1, vr2, vr3, vr4 |
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VGFMA \vr1, \vr2, \vr3, \vr4, 1 |
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.endm |
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.macro VGFMAF vr1, vr2, vr3, vr4 |
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VGFMA \vr1, \vr2, \vr3, \vr4, 2 |
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.endm |
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.macro VGFMAG vr1, vr2, vr3, vr4 |
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VGFMA \vr1, \vr2, \vr3, \vr4, 3 |
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.endm |
|
|
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/* VECTOR SHIFT RIGHT LOGICAL BY BYTE */ |
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.macro VSRLB vr1, vr2, vr3 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC 0, 0x7D, v1, v2, v3 |
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.endm |
|
|
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/* VECTOR REPLICATE IMMEDIATE */ |
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.macro VREPI vr1, imm2, m3 |
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VX_NUM v1, \vr1 |
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.word 0xE700 | ((v1&15) << 4) |
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.word \imm2 |
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MRXBOPC \m3, 0x45, v1 |
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.endm |
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.macro VREPIB vr1, imm2 |
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VREPI \vr1, \imm2, 0 |
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.endm |
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.macro VREPIH vr1, imm2 |
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VREPI \vr1, \imm2, 1 |
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.endm |
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.macro VREPIF vr1, imm2 |
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VREPI \vr1, \imm2, 2 |
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.endm |
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.macro VREPIG vr1, imm2 |
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VREP \vr1, \imm2, 3 |
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.endm |
|
|
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/* VECTOR ADD */ |
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.macro VA vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0xF3, v1, v2, v3 |
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.endm |
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.macro VAB vr1, vr2, vr3 |
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VA \vr1, \vr2, \vr3, 0 |
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.endm |
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.macro VAH vr1, vr2, vr3 |
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VA \vr1, \vr2, \vr3, 1 |
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.endm |
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.macro VAF vr1, vr2, vr3 |
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VA \vr1, \vr2, \vr3, 2 |
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.endm |
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.macro VAG vr1, vr2, vr3 |
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VA \vr1, \vr2, \vr3, 3 |
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.endm |
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.macro VAQ vr1, vr2, vr3 |
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VA \vr1, \vr2, \vr3, 4 |
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.endm |
|
|
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/* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */ |
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.macro VESRAV vr1, vr2, vr3, m4 |
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VX_NUM v1, \vr1 |
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VX_NUM v2, \vr2 |
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VX_NUM v3, \vr3 |
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.word 0xE700 | ((v1&15) << 4) | (v2&15) |
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.word ((v3&15) << 12) |
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MRXBOPC \m4, 0x7A, v1, v2, v3 |
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.endm |
|
|
|
.macro VESRAVB vr1, vr2, vr3 |
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VESRAV \vr1, \vr2, \vr3, 0 |
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.endm |
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.macro VESRAVH vr1, vr2, vr3 |
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VESRAV \vr1, \vr2, \vr3, 1 |
|
.endm |
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.macro VESRAVF vr1, vr2, vr3 |
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VESRAV \vr1, \vr2, \vr3, 2 |
|
.endm |
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.macro VESRAVG vr1, vr2, vr3 |
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VESRAV \vr1, \vr2, \vr3, 3 |
|
.endm |
|
|
|
/* VECTOR ELEMENT ROTATE LEFT LOGICAL */ |
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.macro VERLL vr1, vr3, disp, base="%r0", m4 |
|
VX_NUM v1, \vr1 |
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VX_NUM v3, \vr3 |
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GR_NUM b2, \base |
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.word 0xE700 | ((v1&15) << 4) | (v3&15) |
|
.word (b2 << 12) | (\disp) |
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MRXBOPC \m4, 0x33, v1, v3 |
|
.endm |
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.macro VERLLB vr1, vr3, disp, base="%r0" |
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VERLL \vr1, \vr3, \disp, \base, 0 |
|
.endm |
|
.macro VERLLH vr1, vr3, disp, base="%r0" |
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VERLL \vr1, \vr3, \disp, \base, 1 |
|
.endm |
|
.macro VERLLF vr1, vr3, disp, base="%r0" |
|
VERLL \vr1, \vr3, \disp, \base, 2 |
|
.endm |
|
.macro VERLLG vr1, vr3, disp, base="%r0" |
|
VERLL \vr1, \vr3, \disp, \base, 3 |
|
.endm |
|
|
|
/* VECTOR SHIFT LEFT DOUBLE BY BYTE */ |
|
.macro VSLDB vr1, vr2, vr3, imm4 |
|
VX_NUM v1, \vr1 |
|
VX_NUM v2, \vr2 |
|
VX_NUM v3, \vr3 |
|
.word 0xE700 | ((v1&15) << 4) | (v2&15) |
|
.word ((v3&15) << 12) | (\imm4) |
|
MRXBOPC 0, 0x77, v1, v2, v3 |
|
.endm |
|
|
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#endif /* __ASSEMBLY__ */ |
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#endif /* __ASM_S390_VX_INSN_H */
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