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719 lines
16 KiB
719 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* pxa3xx-gcu.c - Linux kernel module for PXA3xx graphics controllers |
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* |
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* This driver needs a DirectFB counterpart in user space, communication |
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* is handled via mmap()ed memory areas and an ioctl. |
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* |
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* Copyright (c) 2009 Daniel Mack <[email protected]> |
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* Copyright (c) 2009 Janine Kropp <[email protected]> |
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* Copyright (c) 2009 Denis Oliver Kropp <[email protected]> |
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*/ |
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|
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/* |
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* WARNING: This controller is attached to System Bus 2 of the PXA which |
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* needs its arbiter to be enabled explicitly (CKENB & 1<<9). |
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* There is currently no way to do this from Linux, so you need to teach |
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* your bootloader for now. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/miscdevice.h> |
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#include <linux/interrupt.h> |
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#include <linux/spinlock.h> |
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#include <linux/uaccess.h> |
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#include <linux/ioctl.h> |
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#include <linux/delay.h> |
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#include <linux/sched.h> |
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#include <linux/slab.h> |
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#include <linux/clk.h> |
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#include <linux/fs.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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|
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#include "pxa3xx-gcu.h" |
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|
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#define DRV_NAME "pxa3xx-gcu" |
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|
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#define REG_GCCR 0x00 |
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#define GCCR_SYNC_CLR (1 << 9) |
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#define GCCR_BP_RST (1 << 8) |
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#define GCCR_ABORT (1 << 6) |
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#define GCCR_STOP (1 << 4) |
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|
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#define REG_GCISCR 0x04 |
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#define REG_GCIECR 0x08 |
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#define REG_GCRBBR 0x20 |
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#define REG_GCRBLR 0x24 |
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#define REG_GCRBHR 0x28 |
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#define REG_GCRBTR 0x2C |
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#define REG_GCRBEXHR 0x30 |
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|
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#define IE_EOB (1 << 0) |
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#define IE_EEOB (1 << 5) |
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#define IE_ALL 0xff |
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|
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#define SHARED_SIZE PAGE_ALIGN(sizeof(struct pxa3xx_gcu_shared)) |
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|
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/* #define PXA3XX_GCU_DEBUG */ |
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/* #define PXA3XX_GCU_DEBUG_TIMER */ |
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|
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#ifdef PXA3XX_GCU_DEBUG |
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#define QDUMP(msg) \ |
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do { \ |
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QPRINT(priv, KERN_DEBUG, msg); \ |
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} while (0) |
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#else |
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#define QDUMP(msg) do {} while (0) |
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#endif |
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|
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#define QERROR(msg) \ |
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do { \ |
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QPRINT(priv, KERN_ERR, msg); \ |
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} while (0) |
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|
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struct pxa3xx_gcu_batch { |
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struct pxa3xx_gcu_batch *next; |
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u32 *ptr; |
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dma_addr_t phys; |
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unsigned long length; |
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}; |
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|
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struct pxa3xx_gcu_priv { |
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struct device *dev; |
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void __iomem *mmio_base; |
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struct clk *clk; |
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struct pxa3xx_gcu_shared *shared; |
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dma_addr_t shared_phys; |
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struct resource *resource_mem; |
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struct miscdevice misc_dev; |
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wait_queue_head_t wait_idle; |
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wait_queue_head_t wait_free; |
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spinlock_t spinlock; |
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struct timespec64 base_time; |
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|
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struct pxa3xx_gcu_batch *free; |
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struct pxa3xx_gcu_batch *ready; |
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struct pxa3xx_gcu_batch *ready_last; |
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struct pxa3xx_gcu_batch *running; |
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}; |
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|
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static inline unsigned long |
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gc_readl(struct pxa3xx_gcu_priv *priv, unsigned int off) |
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{ |
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return __raw_readl(priv->mmio_base + off); |
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} |
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|
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static inline void |
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gc_writel(struct pxa3xx_gcu_priv *priv, unsigned int off, unsigned long val) |
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{ |
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__raw_writel(val, priv->mmio_base + off); |
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} |
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|
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#define QPRINT(priv, level, msg) \ |
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do { \ |
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struct timespec64 ts; \ |
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struct pxa3xx_gcu_shared *shared = priv->shared; \ |
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u32 base = gc_readl(priv, REG_GCRBBR); \ |
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\ |
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ktime_get_ts64(&ts); \ |
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ts = timespec64_sub(ts, priv->base_time); \ |
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\ |
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printk(level "%lld.%03ld.%03ld - %-17s: %-21s (%s, " \ |
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"STATUS " \ |
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"0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, " \ |
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"T %5ld)\n", \ |
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(s64)(ts.tv_sec), \ |
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ts.tv_nsec / NSEC_PER_MSEC, \ |
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(ts.tv_nsec % NSEC_PER_MSEC) / USEC_PER_MSEC, \ |
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__func__, msg, \ |
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shared->hw_running ? "running" : " idle", \ |
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gc_readl(priv, REG_GCISCR), \ |
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gc_readl(priv, REG_GCRBBR), \ |
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gc_readl(priv, REG_GCRBLR), \ |
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(gc_readl(priv, REG_GCRBEXHR) - base) / 4, \ |
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(gc_readl(priv, REG_GCRBHR) - base) / 4, \ |
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(gc_readl(priv, REG_GCRBTR) - base) / 4); \ |
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} while (0) |
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|
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static void |
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pxa3xx_gcu_reset(struct pxa3xx_gcu_priv *priv) |
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{ |
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QDUMP("RESET"); |
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|
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/* disable interrupts */ |
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gc_writel(priv, REG_GCIECR, 0); |
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|
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/* reset hardware */ |
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gc_writel(priv, REG_GCCR, GCCR_ABORT); |
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gc_writel(priv, REG_GCCR, 0); |
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|
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memset(priv->shared, 0, SHARED_SIZE); |
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priv->shared->buffer_phys = priv->shared_phys; |
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priv->shared->magic = PXA3XX_GCU_SHARED_MAGIC; |
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|
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ktime_get_ts64(&priv->base_time); |
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|
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/* set up the ring buffer pointers */ |
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gc_writel(priv, REG_GCRBLR, 0); |
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gc_writel(priv, REG_GCRBBR, priv->shared_phys); |
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gc_writel(priv, REG_GCRBTR, priv->shared_phys); |
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|
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/* enable all IRQs except EOB */ |
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gc_writel(priv, REG_GCIECR, IE_ALL & ~IE_EOB); |
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} |
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|
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static void |
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dump_whole_state(struct pxa3xx_gcu_priv *priv) |
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{ |
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struct pxa3xx_gcu_shared *sh = priv->shared; |
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u32 base = gc_readl(priv, REG_GCRBBR); |
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|
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QDUMP("DUMP"); |
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|
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printk(KERN_DEBUG "== PXA3XX-GCU DUMP ==\n" |
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"%s, STATUS 0x%02lx, B 0x%08lx [%ld], E %5ld, H %5ld, T %5ld\n", |
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sh->hw_running ? "running" : "idle ", |
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gc_readl(priv, REG_GCISCR), |
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gc_readl(priv, REG_GCRBBR), |
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gc_readl(priv, REG_GCRBLR), |
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(gc_readl(priv, REG_GCRBEXHR) - base) / 4, |
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(gc_readl(priv, REG_GCRBHR) - base) / 4, |
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(gc_readl(priv, REG_GCRBTR) - base) / 4); |
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} |
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|
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static void |
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flush_running(struct pxa3xx_gcu_priv *priv) |
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{ |
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struct pxa3xx_gcu_batch *running = priv->running; |
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struct pxa3xx_gcu_batch *next; |
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|
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while (running) { |
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next = running->next; |
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running->next = priv->free; |
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priv->free = running; |
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running = next; |
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} |
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|
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priv->running = NULL; |
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} |
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|
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static void |
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run_ready(struct pxa3xx_gcu_priv *priv) |
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{ |
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unsigned int num = 0; |
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struct pxa3xx_gcu_shared *shared = priv->shared; |
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struct pxa3xx_gcu_batch *ready = priv->ready; |
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|
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QDUMP("Start"); |
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|
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BUG_ON(!ready); |
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shared->buffer[num++] = 0x05000000; |
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|
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while (ready) { |
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shared->buffer[num++] = 0x00000001; |
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shared->buffer[num++] = ready->phys; |
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ready = ready->next; |
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} |
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shared->buffer[num++] = 0x05000000; |
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priv->running = priv->ready; |
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priv->ready = priv->ready_last = NULL; |
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gc_writel(priv, REG_GCRBLR, 0); |
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shared->hw_running = 1; |
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|
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/* ring base address */ |
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gc_writel(priv, REG_GCRBBR, shared->buffer_phys); |
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|
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/* ring tail address */ |
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gc_writel(priv, REG_GCRBTR, shared->buffer_phys + num * 4); |
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|
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/* ring length */ |
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gc_writel(priv, REG_GCRBLR, ((num + 63) & ~63) * 4); |
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} |
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|
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static irqreturn_t |
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pxa3xx_gcu_handle_irq(int irq, void *ctx) |
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{ |
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struct pxa3xx_gcu_priv *priv = ctx; |
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struct pxa3xx_gcu_shared *shared = priv->shared; |
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u32 status = gc_readl(priv, REG_GCISCR) & IE_ALL; |
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QDUMP("-Interrupt"); |
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if (!status) |
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return IRQ_NONE; |
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spin_lock(&priv->spinlock); |
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shared->num_interrupts++; |
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if (status & IE_EEOB) { |
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QDUMP(" [EEOB]"); |
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flush_running(priv); |
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wake_up_all(&priv->wait_free); |
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|
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if (priv->ready) { |
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run_ready(priv); |
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} else { |
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/* There is no more data prepared by the userspace. |
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* Set hw_running = 0 and wait for the next userspace |
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* kick-off */ |
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shared->num_idle++; |
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shared->hw_running = 0; |
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|
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QDUMP(" '-> Idle."); |
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|
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/* set ring buffer length to zero */ |
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gc_writel(priv, REG_GCRBLR, 0); |
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|
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wake_up_all(&priv->wait_idle); |
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} |
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shared->num_done++; |
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} else { |
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QERROR(" [???]"); |
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dump_whole_state(priv); |
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} |
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|
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/* Clear the interrupt */ |
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gc_writel(priv, REG_GCISCR, status); |
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spin_unlock(&priv->spinlock); |
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|
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return IRQ_HANDLED; |
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} |
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static int |
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pxa3xx_gcu_wait_idle(struct pxa3xx_gcu_priv *priv) |
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{ |
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int ret = 0; |
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QDUMP("Waiting for idle..."); |
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/* Does not need to be atomic. There's a lock in user space, |
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* but anyhow, this is just for statistics. */ |
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priv->shared->num_wait_idle++; |
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|
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while (priv->shared->hw_running) { |
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int num = priv->shared->num_interrupts; |
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u32 rbexhr = gc_readl(priv, REG_GCRBEXHR); |
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ret = wait_event_interruptible_timeout(priv->wait_idle, |
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!priv->shared->hw_running, HZ*4); |
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if (ret != 0) |
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break; |
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if (gc_readl(priv, REG_GCRBEXHR) == rbexhr && |
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priv->shared->num_interrupts == num) { |
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QERROR("TIMEOUT"); |
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ret = -ETIMEDOUT; |
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break; |
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} |
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} |
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QDUMP("done"); |
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|
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return ret; |
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} |
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|
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static int |
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pxa3xx_gcu_wait_free(struct pxa3xx_gcu_priv *priv) |
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{ |
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int ret = 0; |
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QDUMP("Waiting for free..."); |
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|
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/* Does not need to be atomic. There's a lock in user space, |
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* but anyhow, this is just for statistics. */ |
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priv->shared->num_wait_free++; |
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|
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while (!priv->free) { |
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u32 rbexhr = gc_readl(priv, REG_GCRBEXHR); |
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ret = wait_event_interruptible_timeout(priv->wait_free, |
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priv->free, HZ*4); |
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if (ret < 0) |
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break; |
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if (ret > 0) |
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continue; |
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if (gc_readl(priv, REG_GCRBEXHR) == rbexhr) { |
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QERROR("TIMEOUT"); |
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ret = -ETIMEDOUT; |
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break; |
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} |
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} |
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QDUMP("done"); |
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return ret; |
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} |
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|
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/* Misc device layer */ |
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|
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static inline struct pxa3xx_gcu_priv *to_pxa3xx_gcu_priv(struct file *file) |
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{ |
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struct miscdevice *dev = file->private_data; |
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return container_of(dev, struct pxa3xx_gcu_priv, misc_dev); |
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} |
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|
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/* |
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* provide an empty .open callback, so the core sets file->private_data |
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* for us. |
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*/ |
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static int pxa3xx_gcu_open(struct inode *inode, struct file *file) |
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{ |
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return 0; |
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} |
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|
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static ssize_t |
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pxa3xx_gcu_write(struct file *file, const char *buff, |
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size_t count, loff_t *offp) |
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{ |
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int ret; |
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unsigned long flags; |
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struct pxa3xx_gcu_batch *buffer; |
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struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file); |
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|
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int words = count / 4; |
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|
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/* Does not need to be atomic. There's a lock in user space, |
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* but anyhow, this is just for statistics. */ |
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priv->shared->num_writes++; |
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priv->shared->num_words += words; |
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|
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/* Last word reserved for batch buffer end command */ |
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if (words >= PXA3XX_GCU_BATCH_WORDS) |
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return -E2BIG; |
|
|
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/* Wait for a free buffer */ |
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if (!priv->free) { |
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ret = pxa3xx_gcu_wait_free(priv); |
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if (ret < 0) |
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return ret; |
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} |
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|
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/* |
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* Get buffer from free list |
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*/ |
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spin_lock_irqsave(&priv->spinlock, flags); |
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buffer = priv->free; |
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priv->free = buffer->next; |
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spin_unlock_irqrestore(&priv->spinlock, flags); |
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|
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|
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/* Copy data from user into buffer */ |
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ret = copy_from_user(buffer->ptr, buff, words * 4); |
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if (ret) { |
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spin_lock_irqsave(&priv->spinlock, flags); |
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buffer->next = priv->free; |
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priv->free = buffer; |
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spin_unlock_irqrestore(&priv->spinlock, flags); |
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return -EFAULT; |
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} |
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|
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buffer->length = words; |
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|
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/* Append batch buffer end command */ |
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buffer->ptr[words] = 0x01000000; |
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|
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/* |
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* Add buffer to ready list |
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*/ |
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spin_lock_irqsave(&priv->spinlock, flags); |
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|
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buffer->next = NULL; |
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|
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if (priv->ready) { |
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BUG_ON(priv->ready_last == NULL); |
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|
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priv->ready_last->next = buffer; |
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} else |
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priv->ready = buffer; |
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|
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priv->ready_last = buffer; |
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|
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if (!priv->shared->hw_running) |
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run_ready(priv); |
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spin_unlock_irqrestore(&priv->spinlock, flags); |
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|
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return words * 4; |
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} |
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|
|
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static long |
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pxa3xx_gcu_ioctl(struct file *file, unsigned int cmd, unsigned long arg) |
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{ |
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unsigned long flags; |
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struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file); |
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|
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switch (cmd) { |
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case PXA3XX_GCU_IOCTL_RESET: |
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spin_lock_irqsave(&priv->spinlock, flags); |
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pxa3xx_gcu_reset(priv); |
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spin_unlock_irqrestore(&priv->spinlock, flags); |
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return 0; |
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|
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case PXA3XX_GCU_IOCTL_WAIT_IDLE: |
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return pxa3xx_gcu_wait_idle(priv); |
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} |
|
|
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return -ENOSYS; |
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} |
|
|
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static int |
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pxa3xx_gcu_mmap(struct file *file, struct vm_area_struct *vma) |
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{ |
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unsigned int size = vma->vm_end - vma->vm_start; |
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struct pxa3xx_gcu_priv *priv = to_pxa3xx_gcu_priv(file); |
|
|
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switch (vma->vm_pgoff) { |
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case 0: |
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/* hand out the shared data area */ |
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if (size != SHARED_SIZE) |
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return -EINVAL; |
|
|
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return dma_mmap_coherent(priv->dev, vma, |
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priv->shared, priv->shared_phys, size); |
|
|
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case SHARED_SIZE >> PAGE_SHIFT: |
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/* hand out the MMIO base for direct register access |
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* from userspace */ |
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if (size != resource_size(priv->resource_mem)) |
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return -EINVAL; |
|
|
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
|
|
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return io_remap_pfn_range(vma, vma->vm_start, |
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priv->resource_mem->start >> PAGE_SHIFT, |
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size, vma->vm_page_prot); |
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} |
|
|
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return -EINVAL; |
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} |
|
|
|
|
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#ifdef PXA3XX_GCU_DEBUG_TIMER |
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static struct timer_list pxa3xx_gcu_debug_timer; |
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static struct pxa3xx_gcu_priv *debug_timer_priv; |
|
|
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static void pxa3xx_gcu_debug_timedout(struct timer_list *unused) |
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{ |
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struct pxa3xx_gcu_priv *priv = debug_timer_priv; |
|
|
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QERROR("Timer DUMP"); |
|
|
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mod_timer(&pxa3xx_gcu_debug_timer, jiffies + 5 * HZ); |
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} |
|
|
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static void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv) |
|
{ |
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/* init the timer structure */ |
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debug_timer_priv = priv; |
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timer_setup(&pxa3xx_gcu_debug_timer, pxa3xx_gcu_debug_timedout, 0); |
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pxa3xx_gcu_debug_timedout(NULL); |
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} |
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#else |
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static inline void pxa3xx_gcu_init_debug_timer(struct pxa3xx_gcu_priv *priv) {} |
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#endif |
|
|
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static int |
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pxa3xx_gcu_add_buffer(struct device *dev, |
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struct pxa3xx_gcu_priv *priv) |
|
{ |
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struct pxa3xx_gcu_batch *buffer; |
|
|
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buffer = kzalloc(sizeof(struct pxa3xx_gcu_batch), GFP_KERNEL); |
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if (!buffer) |
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return -ENOMEM; |
|
|
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buffer->ptr = dma_alloc_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4, |
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&buffer->phys, GFP_KERNEL); |
|
if (!buffer->ptr) { |
|
kfree(buffer); |
|
return -ENOMEM; |
|
} |
|
|
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buffer->next = priv->free; |
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priv->free = buffer; |
|
|
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return 0; |
|
} |
|
|
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static void |
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pxa3xx_gcu_free_buffers(struct device *dev, |
|
struct pxa3xx_gcu_priv *priv) |
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{ |
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struct pxa3xx_gcu_batch *next, *buffer = priv->free; |
|
|
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while (buffer) { |
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next = buffer->next; |
|
|
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dma_free_coherent(dev, PXA3XX_GCU_BATCH_WORDS * 4, |
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buffer->ptr, buffer->phys); |
|
|
|
kfree(buffer); |
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buffer = next; |
|
} |
|
|
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priv->free = NULL; |
|
} |
|
|
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static const struct file_operations pxa3xx_gcu_miscdev_fops = { |
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.owner = THIS_MODULE, |
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.open = pxa3xx_gcu_open, |
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.write = pxa3xx_gcu_write, |
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.unlocked_ioctl = pxa3xx_gcu_ioctl, |
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.mmap = pxa3xx_gcu_mmap, |
|
}; |
|
|
|
static int pxa3xx_gcu_probe(struct platform_device *pdev) |
|
{ |
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int i, ret, irq; |
|
struct resource *r; |
|
struct pxa3xx_gcu_priv *priv; |
|
struct device *dev = &pdev->dev; |
|
|
|
priv = devm_kzalloc(dev, sizeof(struct pxa3xx_gcu_priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
init_waitqueue_head(&priv->wait_idle); |
|
init_waitqueue_head(&priv->wait_free); |
|
spin_lock_init(&priv->spinlock); |
|
|
|
/* we allocate the misc device structure as part of our own allocation, |
|
* so we can get a pointer to our priv structure later on with |
|
* container_of(). This isn't really necessary as we have a fixed minor |
|
* number anyway, but this is to avoid statics. */ |
|
|
|
priv->misc_dev.minor = PXA3XX_GCU_MINOR, |
|
priv->misc_dev.name = DRV_NAME, |
|
priv->misc_dev.fops = &pxa3xx_gcu_miscdev_fops; |
|
|
|
/* handle IO resources */ |
|
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
priv->mmio_base = devm_ioremap_resource(dev, r); |
|
if (IS_ERR(priv->mmio_base)) |
|
return PTR_ERR(priv->mmio_base); |
|
|
|
/* enable the clock */ |
|
priv->clk = devm_clk_get(dev, NULL); |
|
if (IS_ERR(priv->clk)) { |
|
dev_err(dev, "failed to get clock\n"); |
|
return PTR_ERR(priv->clk); |
|
} |
|
|
|
/* request the IRQ */ |
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
dev_err(dev, "no IRQ defined: %d\n", irq); |
|
return irq; |
|
} |
|
|
|
ret = devm_request_irq(dev, irq, pxa3xx_gcu_handle_irq, |
|
0, DRV_NAME, priv); |
|
if (ret < 0) { |
|
dev_err(dev, "request_irq failed\n"); |
|
return ret; |
|
} |
|
|
|
/* allocate dma memory */ |
|
priv->shared = dma_alloc_coherent(dev, SHARED_SIZE, |
|
&priv->shared_phys, GFP_KERNEL); |
|
if (!priv->shared) { |
|
dev_err(dev, "failed to allocate DMA memory\n"); |
|
return -ENOMEM; |
|
} |
|
|
|
/* register misc device */ |
|
ret = misc_register(&priv->misc_dev); |
|
if (ret < 0) { |
|
dev_err(dev, "misc_register() for minor %d failed\n", |
|
PXA3XX_GCU_MINOR); |
|
goto err_free_dma; |
|
} |
|
|
|
ret = clk_prepare_enable(priv->clk); |
|
if (ret < 0) { |
|
dev_err(dev, "failed to enable clock\n"); |
|
goto err_misc_deregister; |
|
} |
|
|
|
for (i = 0; i < 8; i++) { |
|
ret = pxa3xx_gcu_add_buffer(dev, priv); |
|
if (ret) { |
|
dev_err(dev, "failed to allocate DMA memory\n"); |
|
goto err_disable_clk; |
|
} |
|
} |
|
|
|
platform_set_drvdata(pdev, priv); |
|
priv->resource_mem = r; |
|
priv->dev = dev; |
|
pxa3xx_gcu_reset(priv); |
|
pxa3xx_gcu_init_debug_timer(priv); |
|
|
|
dev_info(dev, "registered @0x%p, DMA 0x%p (%d bytes), IRQ %d\n", |
|
(void *) r->start, (void *) priv->shared_phys, |
|
SHARED_SIZE, irq); |
|
return 0; |
|
|
|
err_free_dma: |
|
dma_free_coherent(dev, SHARED_SIZE, |
|
priv->shared, priv->shared_phys); |
|
|
|
err_misc_deregister: |
|
misc_deregister(&priv->misc_dev); |
|
|
|
err_disable_clk: |
|
clk_disable_unprepare(priv->clk); |
|
|
|
return ret; |
|
} |
|
|
|
static int pxa3xx_gcu_remove(struct platform_device *pdev) |
|
{ |
|
struct pxa3xx_gcu_priv *priv = platform_get_drvdata(pdev); |
|
struct device *dev = &pdev->dev; |
|
|
|
pxa3xx_gcu_wait_idle(priv); |
|
misc_deregister(&priv->misc_dev); |
|
dma_free_coherent(dev, SHARED_SIZE, priv->shared, priv->shared_phys); |
|
pxa3xx_gcu_free_buffers(dev, priv); |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id pxa3xx_gcu_of_match[] = { |
|
{ .compatible = "marvell,pxa300-gcu", }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, pxa3xx_gcu_of_match); |
|
#endif |
|
|
|
static struct platform_driver pxa3xx_gcu_driver = { |
|
.probe = pxa3xx_gcu_probe, |
|
.remove = pxa3xx_gcu_remove, |
|
.driver = { |
|
.name = DRV_NAME, |
|
.of_match_table = of_match_ptr(pxa3xx_gcu_of_match), |
|
}, |
|
}; |
|
|
|
module_platform_driver(pxa3xx_gcu_driver); |
|
|
|
MODULE_DESCRIPTION("PXA3xx graphics controller unit driver"); |
|
MODULE_LICENSE("GPL"); |
|
MODULE_ALIAS_MISCDEV(PXA3XX_GCU_MINOR); |
|
MODULE_AUTHOR("Janine Kropp <[email protected]>, " |
|
"Denis Oliver Kropp <[email protected]>, " |
|
"Daniel Mack <[email protected]>");
|
|
|