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323 lines
9.5 KiB
323 lines
9.5 KiB
/* |
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* linux/drivers/video/kyro/STG4000InitDevice.c |
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* |
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* Copyright (C) 2000 Imagination Technologies Ltd |
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* Copyright (C) 2002 STMicroelectronics |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file COPYING in the main directory of this archive |
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* for more details. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include "STG4000Reg.h" |
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#include "STG4000Interface.h" |
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/* SDRAM fixed settings */ |
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#define SDRAM_CFG_0 0x49A1 |
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#define SDRAM_CFG_1 0xA732 |
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#define SDRAM_CFG_2 0x31 |
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#define SDRAM_ARB_CFG 0xA0 |
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#define SDRAM_REFRESH 0x20 |
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/* Reset values */ |
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#define PMX2_SOFTRESET_DAC_RST 0x0001 |
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#define PMX2_SOFTRESET_C1_RST 0x0004 |
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#define PMX2_SOFTRESET_C2_RST 0x0008 |
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#define PMX2_SOFTRESET_3D_RST 0x0010 |
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#define PMX2_SOFTRESET_VIDIN_RST 0x0020 |
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#define PMX2_SOFTRESET_TLB_RST 0x0040 |
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#define PMX2_SOFTRESET_SD_RST 0x0080 |
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#define PMX2_SOFTRESET_VGA_RST 0x0100 |
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#define PMX2_SOFTRESET_ROM_RST 0x0200 /* reserved bit, do not reset */ |
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#define PMX2_SOFTRESET_TA_RST 0x0400 |
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#define PMX2_SOFTRESET_REG_RST 0x4000 |
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#define PMX2_SOFTRESET_ALL 0x7fff |
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/* Core clock freq */ |
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#define CORE_PLL_FREQ 1000000 |
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/* Reference Clock freq */ |
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#define REF_FREQ 14318 |
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/* PCI Registers */ |
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static u16 CorePllControl = 0x70; |
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#define PCI_CONFIG_SUBSYS_ID 0x2e |
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/* Misc */ |
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#define CORE_PLL_MODE_REG_0_7 3 |
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#define CORE_PLL_MODE_REG_8_15 2 |
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#define CORE_PLL_MODE_CONFIG_REG 1 |
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#define DAC_PLL_CONFIG_REG 0 |
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#define STG_MAX_VCO 500000 |
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#define STG_MIN_VCO 100000 |
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/* PLL Clock */ |
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#define STG4K3_PLL_SCALER 8 /* scale numbers by 2^8 for fixed point calc */ |
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#define STG4K3_PLL_MIN_R 2 /* Minimum multiplier */ |
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#define STG4K3_PLL_MAX_R 33 /* Max */ |
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#define STG4K3_PLL_MIN_F 2 /* Minimum divisor */ |
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#define STG4K3_PLL_MAX_F 513 /* Max */ |
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#define STG4K3_PLL_MIN_OD 0 /* Min output divider (shift) */ |
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#define STG4K3_PLL_MAX_OD 2 /* Max */ |
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#define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */ |
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#define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */ |
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#define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */ |
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#define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */ |
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#define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */ |
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#define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */ |
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#define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */ |
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#define OS_DELAY(X) \ |
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{ \ |
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volatile u32 i,count=0; \ |
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for(i=0;i<X;i++) count++; \ |
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} |
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static u32 InitSDRAMRegisters(volatile STG4000REG __iomem *pSTGReg, |
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u32 dwSubSysID, u32 dwRevID) |
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{ |
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u32 adwSDRAMArgCfg0[] = { 0xa0, 0x80, 0xa0, 0xa0, 0xa0 }; |
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u32 adwSDRAMCfg1[] = { 0x8732, 0x8732, 0xa732, 0xa732, 0x8732 }; |
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u32 adwSDRAMCfg2[] = { 0x87d2, 0x87d2, 0xa7d2, 0x87d2, 0xa7d2 }; |
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u32 adwSDRAMRsh[] = { 36, 39, 40 }; |
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u32 adwChipSpeed[] = { 110, 120, 125 }; |
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u32 dwMemTypeIdx; |
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u32 dwChipSpeedIdx; |
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/* Get memory tpye and chip speed indexs from the SubSysDevID */ |
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dwMemTypeIdx = (dwSubSysID & 0x70) >> 4; |
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dwChipSpeedIdx = (dwSubSysID & 0x180) >> 7; |
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if (dwMemTypeIdx > 4 || dwChipSpeedIdx > 2) |
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return 0; |
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/* Program SD-RAM interface */ |
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STG_WRITE_REG(SDRAMArbiterConf, adwSDRAMArgCfg0[dwMemTypeIdx]); |
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if (dwRevID < 5) { |
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STG_WRITE_REG(SDRAMConf0, 0x49A1); |
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STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg1[dwMemTypeIdx]); |
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} else { |
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STG_WRITE_REG(SDRAMConf0, 0x4DF1); |
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STG_WRITE_REG(SDRAMConf1, adwSDRAMCfg2[dwMemTypeIdx]); |
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} |
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STG_WRITE_REG(SDRAMConf2, 0x31); |
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STG_WRITE_REG(SDRAMRefresh, adwSDRAMRsh[dwChipSpeedIdx]); |
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return adwChipSpeed[dwChipSpeedIdx] * 10000; |
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} |
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u32 ProgramClock(u32 refClock, |
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u32 coreClock, |
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u32 * FOut, u32 * ROut, u32 * POut) |
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{ |
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u32 R = 0, F = 0, OD = 0, ODIndex = 0; |
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u32 ulBestR = 0, ulBestF = 0, ulBestOD = 0; |
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u32 ulBestClk = 0, ulBestScore = 0; |
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u32 ulScore, ulPhaseScore, ulVcoScore; |
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u32 ulTmp = 0, ulVCO; |
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u32 ulScaleClockReq, ulMinClock, ulMaxClock; |
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u32 ODValues[] = { 1, 2, 0 }; |
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/* Translate clock in Hz */ |
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coreClock *= 100; /* in Hz */ |
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refClock *= 1000; /* in Hz */ |
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/* Work out acceptable clock |
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* The method calculates ~ +- 0.4% (1/256) |
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*/ |
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ulMinClock = coreClock - (coreClock >> 8); |
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ulMaxClock = coreClock + (coreClock >> 8); |
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/* Scale clock required for use in calculations */ |
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ulScaleClockReq = coreClock >> STG4K3_PLL_SCALER; |
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/* Iterate through post divider values */ |
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for (ODIndex = 0; ODIndex < 3; ODIndex++) { |
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OD = ODValues[ODIndex]; |
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R = STG4K3_PLL_MIN_R; |
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/* loop for pre-divider from min to max */ |
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while (R <= STG4K3_PLL_MAX_R) { |
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/* estimate required feedback multiplier */ |
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ulTmp = R * (ulScaleClockReq << OD); |
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/* F = ClkRequired * R * (2^OD) / Fref */ |
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F = (u32)(ulTmp / (refClock >> STG4K3_PLL_SCALER)); |
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/* compensate for accuracy */ |
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if (F > STG4K3_PLL_MIN_F) |
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F--; |
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/* |
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* We should be close to our target frequency (if it's |
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* achievable with current OD & R) let's iterate |
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* through F for best fit |
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*/ |
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while ((F >= STG4K3_PLL_MIN_F) && |
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(F <= STG4K3_PLL_MAX_F)) { |
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/* Calc VCO at full accuracy */ |
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ulVCO = refClock / R; |
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ulVCO = F * ulVCO; |
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/* |
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* Check it's within restricted VCO range |
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* unless of course the desired frequency is |
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* above the restricted range, then test |
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* against VCO limit |
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*/ |
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if ((ulVCO >= STG4K3_PLL_MINR_VCO) && |
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((ulVCO <= STG4K3_PLL_MAXR_VCO) || |
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((coreClock > STG4K3_PLL_MAXR_VCO) |
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&& (ulVCO <= STG4K3_PLL_MAX_VCO)))) { |
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ulTmp = (ulVCO >> OD); /* Clock = VCO / (2^OD) */ |
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/* Is this clock good enough? */ |
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if ((ulTmp >= ulMinClock) |
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&& (ulTmp <= ulMaxClock)) { |
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ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K3_PLL_MAX_R)) >> 10); |
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ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10); |
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ulScore = ulPhaseScore + ulVcoScore; |
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if (!ulBestScore) { |
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ulBestOD = OD; |
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ulBestF = F; |
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ulBestR = R; |
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ulBestClk = ulTmp; |
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ulBestScore = |
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ulScore; |
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} |
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/* is this better, ( aim for highest Score) */ |
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/*-------------------------------------------------------------------------- |
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Here we want to use a scoring system which will take account of both the |
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value at the phase comparater and the VCO output |
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to do this we will use a cumulative score between the two |
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The way this ends up is that we choose the first value in the loop anyway |
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but we shall keep this code in case new restrictions come into play |
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--------------------------------------------------------------------------*/ |
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if ((ulScore >= ulBestScore) && (OD > 0)) { |
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ulBestOD = OD; |
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ulBestF = F; |
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ulBestR = R; |
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ulBestClk = ulTmp; |
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ulBestScore = |
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ulScore; |
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} |
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} |
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} |
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F++; |
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} |
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R++; |
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} |
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} |
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/* |
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did we find anything? |
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Then return RFOD |
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*/ |
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if (ulBestScore) { |
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*ROut = ulBestR; |
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*FOut = ulBestF; |
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if ((ulBestOD == 2) || (ulBestOD == 3)) { |
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*POut = 3; |
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} else |
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*POut = ulBestOD; |
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} |
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return (ulBestClk); |
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} |
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int SetCoreClockPLL(volatile STG4000REG __iomem *pSTGReg, struct pci_dev *pDev) |
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{ |
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u32 F, R, P; |
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u16 core_pll = 0, sub; |
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u32 tmp; |
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u32 ulChipSpeed; |
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STG_WRITE_REG(IntMask, 0xFFFF); |
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/* Disable Primary Core Thread0 */ |
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tmp = STG_READ_REG(Thread0Enable); |
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CLEAR_BIT(0); |
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STG_WRITE_REG(Thread0Enable, tmp); |
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/* Disable Primary Core Thread1 */ |
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tmp = STG_READ_REG(Thread1Enable); |
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CLEAR_BIT(0); |
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STG_WRITE_REG(Thread1Enable, tmp); |
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STG_WRITE_REG(SoftwareReset, |
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PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST); |
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STG_WRITE_REG(SoftwareReset, |
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PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST | |
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PMX2_SOFTRESET_ROM_RST); |
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/* Need to play around to reset TA */ |
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STG_WRITE_REG(TAConfiguration, 0); |
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STG_WRITE_REG(SoftwareReset, |
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PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_ROM_RST); |
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STG_WRITE_REG(SoftwareReset, |
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PMX2_SOFTRESET_REG_RST | PMX2_SOFTRESET_TA_RST | |
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PMX2_SOFTRESET_ROM_RST); |
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pci_read_config_word(pDev, PCI_CONFIG_SUBSYS_ID, &sub); |
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ulChipSpeed = InitSDRAMRegisters(pSTGReg, (u32)sub, |
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(u32)pDev->revision); |
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if (ulChipSpeed == 0) |
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return -EINVAL; |
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ProgramClock(REF_FREQ, CORE_PLL_FREQ, &F, &R, &P); |
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core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); |
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/* Set Core PLL Control to Core PLL Mode */ |
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/* Send bits 0:7 of the Core PLL Mode register */ |
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tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF)); |
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pci_write_config_word(pDev, CorePllControl, tmp); |
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/* Without some delay between the PCI config writes the clock does |
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not reliably set when the code is compiled -O3 |
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*/ |
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OS_DELAY(1000000); |
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tmp |= SET_BIT(14); |
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pci_write_config_word(pDev, CorePllControl, tmp); |
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OS_DELAY(1000000); |
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/* Send bits 8:15 of the Core PLL Mode register */ |
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tmp = |
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((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8)); |
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pci_write_config_word(pDev, CorePllControl, tmp); |
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OS_DELAY(1000000); |
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tmp |= SET_BIT(14); |
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pci_write_config_word(pDev, CorePllControl, tmp); |
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OS_DELAY(1000000); |
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STG_WRITE_REG(SoftwareReset, PMX2_SOFTRESET_ALL); |
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#if 0 |
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/* Enable Primary Core Thread0 */ |
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tmp = ((STG_READ_REG(Thread0Enable)) | SET_BIT(0)); |
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STG_WRITE_REG(Thread0Enable, tmp); |
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/* Enable Primary Core Thread1 */ |
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tmp = ((STG_READ_REG(Thread1Enable)) | SET_BIT(0)); |
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STG_WRITE_REG(Thread1Enable, tmp); |
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#endif |
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return 0; |
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}
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