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838 lines
20 KiB
838 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* Geode LX framebuffer driver |
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* |
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* Copyright (C) 2006-2007, Advanced Micro Devices,Inc. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/fb.h> |
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#include <linux/uaccess.h> |
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#include <linux/delay.h> |
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#include <linux/cs5535.h> |
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#include "lxfb.h" |
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/* TODO |
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* Support panel scaling |
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* Add acceleration |
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* Add support for interlacing (TV out) |
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* Support compression |
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*/ |
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/* This is the complete list of PLL frequencies that we can set - |
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* we will choose the closest match to the incoming clock. |
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* freq is the frequency of the dotclock * 1000 (for example, |
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* 24823 = 24.983 Mhz). |
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* pllval is the corresponding PLL value |
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*/ |
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static const struct { |
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unsigned int pllval; |
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unsigned int freq; |
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} pll_table[] = { |
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{ 0x000131AC, 6231 }, |
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{ 0x0001215D, 6294 }, |
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{ 0x00011087, 6750 }, |
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{ 0x0001216C, 7081 }, |
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{ 0x0001218D, 7140 }, |
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{ 0x000110C9, 7800 }, |
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{ 0x00013147, 7875 }, |
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{ 0x000110A7, 8258 }, |
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{ 0x00012159, 8778 }, |
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{ 0x00014249, 8875 }, |
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{ 0x00010057, 9000 }, |
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{ 0x0001219A, 9472 }, |
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{ 0x00012158, 9792 }, |
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{ 0x00010045, 10000 }, |
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{ 0x00010089, 10791 }, |
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{ 0x000110E7, 11225 }, |
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{ 0x00012136, 11430 }, |
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{ 0x00013207, 12375 }, |
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{ 0x00012187, 12500 }, |
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{ 0x00014286, 14063 }, |
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{ 0x000110E5, 15016 }, |
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{ 0x00014214, 16250 }, |
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{ 0x00011105, 17045 }, |
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{ 0x000131E4, 18563 }, |
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{ 0x00013183, 18750 }, |
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{ 0x00014284, 19688 }, |
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{ 0x00011104, 20400 }, |
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{ 0x00016363, 23625 }, |
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{ 0x000031AC, 24923 }, |
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{ 0x0000215D, 25175 }, |
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{ 0x00001087, 27000 }, |
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{ 0x0000216C, 28322 }, |
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{ 0x0000218D, 28560 }, |
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{ 0x000010C9, 31200 }, |
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{ 0x00003147, 31500 }, |
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{ 0x000010A7, 33032 }, |
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{ 0x00002159, 35112 }, |
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{ 0x00004249, 35500 }, |
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{ 0x00000057, 36000 }, |
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{ 0x0000219A, 37889 }, |
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{ 0x00002158, 39168 }, |
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{ 0x00000045, 40000 }, |
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{ 0x00000089, 43163 }, |
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{ 0x000010E7, 44900 }, |
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{ 0x00002136, 45720 }, |
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{ 0x00003207, 49500 }, |
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{ 0x00002187, 50000 }, |
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{ 0x00004286, 56250 }, |
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{ 0x000010E5, 60065 }, |
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{ 0x00004214, 65000 }, |
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{ 0x00001105, 68179 }, |
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{ 0x000031E4, 74250 }, |
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{ 0x00003183, 75000 }, |
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{ 0x00004284, 78750 }, |
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{ 0x00001104, 81600 }, |
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{ 0x00006363, 94500 }, |
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{ 0x00005303, 97520 }, |
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{ 0x00002183, 100187 }, |
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{ 0x00002122, 101420 }, |
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{ 0x00001081, 108000 }, |
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{ 0x00006201, 113310 }, |
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{ 0x00000041, 119650 }, |
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{ 0x000041A1, 129600 }, |
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{ 0x00002182, 133500 }, |
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{ 0x000041B1, 135000 }, |
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{ 0x00000051, 144000 }, |
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{ 0x000041E1, 148500 }, |
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{ 0x000062D1, 157500 }, |
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{ 0x000031A1, 162000 }, |
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{ 0x00000061, 169203 }, |
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{ 0x00004231, 172800 }, |
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{ 0x00002151, 175500 }, |
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{ 0x000052E1, 189000 }, |
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{ 0x00000071, 192000 }, |
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{ 0x00003201, 198000 }, |
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{ 0x00004291, 202500 }, |
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{ 0x00001101, 204750 }, |
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{ 0x00007481, 218250 }, |
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{ 0x00004170, 229500 }, |
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{ 0x00006210, 234000 }, |
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{ 0x00003140, 251182 }, |
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{ 0x00006250, 261000 }, |
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{ 0x000041C0, 278400 }, |
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{ 0x00005220, 280640 }, |
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{ 0x00000050, 288000 }, |
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{ 0x000041E0, 297000 }, |
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{ 0x00002130, 320207 } |
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}; |
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static void lx_set_dotpll(u32 pllval) |
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{ |
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u32 dotpll_lo, dotpll_hi; |
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int i; |
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rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); |
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if ((dotpll_lo & MSR_GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval)) |
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return; |
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dotpll_hi = pllval; |
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dotpll_lo &= ~(MSR_GLCP_DOTPLL_BYPASS | MSR_GLCP_DOTPLL_HALFPIX); |
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dotpll_lo |= MSR_GLCP_DOTPLL_DOTRESET; |
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wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); |
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/* Wait 100us for the PLL to lock */ |
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udelay(100); |
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/* Now, loop for the lock bit */ |
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for (i = 0; i < 1000; i++) { |
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rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); |
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if (dotpll_lo & MSR_GLCP_DOTPLL_LOCK) |
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break; |
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} |
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/* Clear the reset bit */ |
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dotpll_lo &= ~MSR_GLCP_DOTPLL_DOTRESET; |
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wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi); |
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} |
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/* Set the clock based on the frequency specified by the current mode */ |
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static void lx_set_clock(struct fb_info *info) |
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{ |
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unsigned int diff, min, best = 0; |
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unsigned int freq, i; |
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freq = (unsigned int) (1000000000 / info->var.pixclock); |
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min = abs(pll_table[0].freq - freq); |
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for (i = 0; i < ARRAY_SIZE(pll_table); i++) { |
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diff = abs(pll_table[i].freq - freq); |
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if (diff < min) { |
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min = diff; |
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best = i; |
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} |
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} |
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lx_set_dotpll(pll_table[best].pllval & 0x00017FFF); |
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} |
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static void lx_graphics_disable(struct fb_info *info) |
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{ |
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struct lxfb_par *par = info->par; |
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unsigned int val, gcfg; |
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/* Note: This assumes that the video is in a quitet state */ |
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write_vp(par, VP_A1T, 0); |
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write_vp(par, VP_A2T, 0); |
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write_vp(par, VP_A3T, 0); |
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/* Turn off the VGA and video enable */ |
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val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GENERAL_CFG_VGAE | |
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DC_GENERAL_CFG_VIDE); |
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write_dc(par, DC_GENERAL_CFG, val); |
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val = read_vp(par, VP_VCFG) & ~VP_VCFG_VID_EN; |
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write_vp(par, VP_VCFG, val); |
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write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_IRQ_VIP_VSYNC_LOSS_IRQ_MASK | |
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DC_IRQ_STATUS | DC_IRQ_VIP_VSYNC_IRQ_STATUS); |
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val = read_dc(par, DC_GENLK_CTL) & ~DC_GENLK_CTL_GENLK_EN; |
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write_dc(par, DC_GENLK_CTL, val); |
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val = read_dc(par, DC_CLR_KEY); |
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write_dc(par, DC_CLR_KEY, val & ~DC_CLR_KEY_CLR_KEY_EN); |
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/* turn off the panel */ |
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write_fp(par, FP_PM, read_fp(par, FP_PM) & ~FP_PM_P); |
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val = read_vp(par, VP_MISC) | VP_MISC_DACPWRDN; |
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write_vp(par, VP_MISC, val); |
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/* Turn off the display */ |
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val = read_vp(par, VP_DCFG); |
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write_vp(par, VP_DCFG, val & ~(VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | |
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VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN)); |
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gcfg = read_dc(par, DC_GENERAL_CFG); |
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gcfg &= ~(DC_GENERAL_CFG_CMPE | DC_GENERAL_CFG_DECE); |
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write_dc(par, DC_GENERAL_CFG, gcfg); |
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/* Turn off the TGEN */ |
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val = read_dc(par, DC_DISPLAY_CFG); |
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val &= ~DC_DISPLAY_CFG_TGEN; |
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write_dc(par, DC_DISPLAY_CFG, val); |
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/* Wait 1000 usecs to ensure that the TGEN is clear */ |
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udelay(1000); |
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/* Turn off the FIFO loader */ |
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gcfg &= ~DC_GENERAL_CFG_DFLE; |
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write_dc(par, DC_GENERAL_CFG, gcfg); |
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/* Lastly, wait for the GP to go idle */ |
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do { |
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val = read_gp(par, GP_BLT_STATUS); |
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} while ((val & GP_BLT_STATUS_PB) || !(val & GP_BLT_STATUS_CE)); |
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} |
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static void lx_graphics_enable(struct fb_info *info) |
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{ |
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struct lxfb_par *par = info->par; |
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u32 temp, config; |
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/* Set the video request register */ |
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write_vp(par, VP_VRR, 0); |
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/* Set up the polarities */ |
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config = read_vp(par, VP_DCFG); |
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config &= ~(VP_DCFG_CRT_SYNC_SKW | VP_DCFG_PWR_SEQ_DELAY | |
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VP_DCFG_CRT_HSYNC_POL | VP_DCFG_CRT_VSYNC_POL); |
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config |= (VP_DCFG_CRT_SYNC_SKW_DEFAULT | VP_DCFG_PWR_SEQ_DELAY_DEFAULT |
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| VP_DCFG_GV_GAM); |
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if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) |
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config |= VP_DCFG_CRT_HSYNC_POL; |
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if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) |
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config |= VP_DCFG_CRT_VSYNC_POL; |
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if (par->output & OUTPUT_PANEL) { |
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u32 msrlo, msrhi; |
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write_fp(par, FP_PT1, 0); |
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temp = FP_PT2_SCRC; |
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if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) |
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temp |= FP_PT2_HSP; |
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if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) |
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temp |= FP_PT2_VSP; |
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write_fp(par, FP_PT2, temp); |
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write_fp(par, FP_DFC, FP_DFC_BC); |
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msrlo = MSR_LX_MSR_PADSEL_TFT_SEL_LOW; |
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msrhi = MSR_LX_MSR_PADSEL_TFT_SEL_HIGH; |
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wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi); |
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} |
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if (par->output & OUTPUT_CRT) { |
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config |= VP_DCFG_CRT_EN | VP_DCFG_HSYNC_EN | |
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VP_DCFG_VSYNC_EN | VP_DCFG_DAC_BL_EN; |
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} |
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write_vp(par, VP_DCFG, config); |
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/* Turn the CRT dacs back on */ |
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if (par->output & OUTPUT_CRT) { |
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temp = read_vp(par, VP_MISC); |
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temp &= ~(VP_MISC_DACPWRDN | VP_MISC_APWRDN); |
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write_vp(par, VP_MISC, temp); |
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} |
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/* Turn the panel on (if it isn't already) */ |
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if (par->output & OUTPUT_PANEL) |
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write_fp(par, FP_PM, read_fp(par, FP_PM) | FP_PM_P); |
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} |
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unsigned int lx_framebuffer_size(void) |
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{ |
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unsigned int val; |
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if (!cs5535_has_vsa2()) { |
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uint32_t hi, lo; |
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/* The number of pages is (PMAX - PMIN)+1 */ |
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rdmsr(MSR_GLIU_P2D_RO0, lo, hi); |
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/* PMAX */ |
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val = ((hi & 0xff) << 12) | ((lo & 0xfff00000) >> 20); |
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/* PMIN */ |
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val -= (lo & 0x000fffff); |
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val += 1; |
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/* The page size is 4k */ |
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return (val << 12); |
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} |
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/* The frame buffer size is reported by a VSM in VSA II */ |
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/* Virtual Register Class = 0x02 */ |
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/* VG_MEM_SIZE (1MB units) = 0x00 */ |
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outw(VSA_VR_UNLOCK, VSA_VRC_INDEX); |
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outw(VSA_VR_MEM_SIZE, VSA_VRC_INDEX); |
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val = (unsigned int)(inw(VSA_VRC_DATA)) & 0xFE; |
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return (val << 20); |
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} |
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void lx_set_mode(struct fb_info *info) |
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{ |
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struct lxfb_par *par = info->par; |
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u64 msrval; |
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unsigned int max, dv, val, size; |
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unsigned int gcfg, dcfg; |
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int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal; |
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int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal; |
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/* Unlock the DC registers */ |
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write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); |
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lx_graphics_disable(info); |
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lx_set_clock(info); |
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/* Set output mode */ |
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rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); |
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msrval &= ~MSR_LX_GLD_MSR_CONFIG_FMT; |
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if (par->output & OUTPUT_PANEL) { |
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msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_FP; |
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if (par->output & OUTPUT_CRT) |
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msrval |= MSR_LX_GLD_MSR_CONFIG_FPC; |
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else |
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msrval &= ~MSR_LX_GLD_MSR_CONFIG_FPC; |
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} else |
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msrval |= MSR_LX_GLD_MSR_CONFIG_FMT_CRT; |
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wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval); |
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/* Clear the various buffers */ |
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/* FIXME: Adjust for panning here */ |
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write_dc(par, DC_FB_ST_OFFSET, 0); |
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write_dc(par, DC_CB_ST_OFFSET, 0); |
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write_dc(par, DC_CURS_ST_OFFSET, 0); |
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/* FIXME: Add support for interlacing */ |
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/* FIXME: Add support for scaling */ |
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val = read_dc(par, DC_GENLK_CTL); |
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val &= ~(DC_GENLK_CTL_ALPHA_FLICK_EN | DC_GENLK_CTL_FLICK_EN | |
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DC_GENLK_CTL_FLICK_SEL_MASK); |
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/* Default scaling params */ |
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write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000); |
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write_dc(par, DC_IRQ_FILT_CTL, 0); |
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write_dc(par, DC_GENLK_CTL, val); |
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/* FIXME: Support compression */ |
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if (info->fix.line_length > 4096) |
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dv = DC_DV_CTL_DV_LINE_SIZE_8K; |
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else if (info->fix.line_length > 2048) |
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dv = DC_DV_CTL_DV_LINE_SIZE_4K; |
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else if (info->fix.line_length > 1024) |
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dv = DC_DV_CTL_DV_LINE_SIZE_2K; |
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else |
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dv = DC_DV_CTL_DV_LINE_SIZE_1K; |
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max = info->fix.line_length * info->var.yres; |
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max = (max + 0x3FF) & 0xFFFFFC00; |
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write_dc(par, DC_DV_TOP, max | DC_DV_TOP_DV_TOP_EN); |
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val = read_dc(par, DC_DV_CTL) & ~DC_DV_CTL_DV_LINE_SIZE; |
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write_dc(par, DC_DV_CTL, val | dv); |
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size = info->var.xres * (info->var.bits_per_pixel >> 3); |
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write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3); |
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write_dc(par, DC_LINE_SIZE, (size + 7) >> 3); |
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/* Set default watermark values */ |
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rdmsrl(MSR_LX_SPARE_MSR, msrval); |
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msrval &= ~(MSR_LX_SPARE_MSR_DIS_CFIFO_HGO |
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| MSR_LX_SPARE_MSR_VFIFO_ARB_SEL |
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| MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M |
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| MSR_LX_SPARE_MSR_WM_LPEN_OVRD); |
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msrval |= MSR_LX_SPARE_MSR_DIS_VIFO_WM | |
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MSR_LX_SPARE_MSR_DIS_INIT_V_PRI; |
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wrmsrl(MSR_LX_SPARE_MSR, msrval); |
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gcfg = DC_GENERAL_CFG_DFLE; /* Display fifo enable */ |
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gcfg |= (0x6 << DC_GENERAL_CFG_DFHPSL_SHIFT) | /* default priority */ |
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(0xb << DC_GENERAL_CFG_DFHPEL_SHIFT); |
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gcfg |= DC_GENERAL_CFG_FDTY; /* Set the frame dirty mode */ |
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dcfg = DC_DISPLAY_CFG_VDEN; /* Enable video data */ |
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dcfg |= DC_DISPLAY_CFG_GDEN; /* Enable graphics */ |
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dcfg |= DC_DISPLAY_CFG_TGEN; /* Turn on the timing generator */ |
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dcfg |= DC_DISPLAY_CFG_TRUP; /* Update timings immediately */ |
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dcfg |= DC_DISPLAY_CFG_PALB; /* Palette bypass in > 8 bpp modes */ |
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dcfg |= DC_DISPLAY_CFG_VISL; |
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dcfg |= DC_DISPLAY_CFG_DCEN; /* Always center the display */ |
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|
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/* Set the current BPP mode */ |
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switch (info->var.bits_per_pixel) { |
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case 8: |
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP; |
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break; |
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case 16: |
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP; |
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break; |
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|
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case 32: |
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case 24: |
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dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP; |
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break; |
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} |
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|
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/* Now - set up the timings */ |
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hactive = info->var.xres; |
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hblankstart = hactive; |
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hsyncstart = hblankstart + info->var.right_margin; |
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hsyncend = hsyncstart + info->var.hsync_len; |
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hblankend = hsyncend + info->var.left_margin; |
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htotal = hblankend; |
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vactive = info->var.yres; |
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vblankstart = vactive; |
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vsyncstart = vblankstart + info->var.lower_margin; |
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vsyncend = vsyncstart + info->var.vsync_len; |
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vblankend = vsyncend + info->var.upper_margin; |
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vtotal = vblankend; |
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write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16)); |
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write_dc(par, DC_H_BLANK_TIMING, |
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(hblankstart - 1) | ((hblankend - 1) << 16)); |
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write_dc(par, DC_H_SYNC_TIMING, |
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(hsyncstart - 1) | ((hsyncend - 1) << 16)); |
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write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16)); |
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write_dc(par, DC_V_BLANK_TIMING, |
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(vblankstart - 1) | ((vblankend - 1) << 16)); |
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write_dc(par, DC_V_SYNC_TIMING, |
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(vsyncstart - 1) | ((vsyncend - 1) << 16)); |
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write_dc(par, DC_FB_ACTIVE, |
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(info->var.xres - 1) << 16 | (info->var.yres - 1)); |
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|
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/* And re-enable the graphics output */ |
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lx_graphics_enable(info); |
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|
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/* Write the two main configuration registers */ |
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write_dc(par, DC_DISPLAY_CFG, dcfg); |
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write_dc(par, DC_ARB_CFG, 0); |
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write_dc(par, DC_GENERAL_CFG, gcfg); |
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|
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/* Lock the DC registers */ |
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write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); |
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} |
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|
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void lx_set_palette_reg(struct fb_info *info, unsigned regno, |
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unsigned red, unsigned green, unsigned blue) |
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{ |
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struct lxfb_par *par = info->par; |
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int val; |
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|
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/* Hardware palette is in RGB 8-8-8 format. */ |
|
|
|
val = (red << 8) & 0xff0000; |
|
val |= (green) & 0x00ff00; |
|
val |= (blue >> 8) & 0x0000ff; |
|
|
|
write_dc(par, DC_PAL_ADDRESS, regno); |
|
write_dc(par, DC_PAL_DATA, val); |
|
} |
|
|
|
int lx_blank_display(struct fb_info *info, int blank_mode) |
|
{ |
|
struct lxfb_par *par = info->par; |
|
u32 dcfg, misc, fp_pm; |
|
int blank, hsync, vsync; |
|
|
|
/* CRT power saving modes. */ |
|
switch (blank_mode) { |
|
case FB_BLANK_UNBLANK: |
|
blank = 0; hsync = 1; vsync = 1; |
|
break; |
|
case FB_BLANK_NORMAL: |
|
blank = 1; hsync = 1; vsync = 1; |
|
break; |
|
case FB_BLANK_VSYNC_SUSPEND: |
|
blank = 1; hsync = 1; vsync = 0; |
|
break; |
|
case FB_BLANK_HSYNC_SUSPEND: |
|
blank = 1; hsync = 0; vsync = 1; |
|
break; |
|
case FB_BLANK_POWERDOWN: |
|
blank = 1; hsync = 0; vsync = 0; |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
dcfg = read_vp(par, VP_DCFG); |
|
dcfg &= ~(VP_DCFG_DAC_BL_EN | VP_DCFG_HSYNC_EN | VP_DCFG_VSYNC_EN | |
|
VP_DCFG_CRT_EN); |
|
if (!blank) |
|
dcfg |= VP_DCFG_DAC_BL_EN | VP_DCFG_CRT_EN; |
|
if (hsync) |
|
dcfg |= VP_DCFG_HSYNC_EN; |
|
if (vsync) |
|
dcfg |= VP_DCFG_VSYNC_EN; |
|
|
|
write_vp(par, VP_DCFG, dcfg); |
|
|
|
misc = read_vp(par, VP_MISC); |
|
|
|
if (vsync && hsync) |
|
misc &= ~VP_MISC_DACPWRDN; |
|
else |
|
misc |= VP_MISC_DACPWRDN; |
|
|
|
write_vp(par, VP_MISC, misc); |
|
|
|
/* Power on/off flat panel */ |
|
|
|
if (par->output & OUTPUT_PANEL) { |
|
fp_pm = read_fp(par, FP_PM); |
|
if (blank_mode == FB_BLANK_POWERDOWN) |
|
fp_pm &= ~FP_PM_P; |
|
else |
|
fp_pm |= FP_PM_P; |
|
write_fp(par, FP_PM, fp_pm); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static void lx_save_regs(struct lxfb_par *par) |
|
{ |
|
uint32_t filt; |
|
int i; |
|
|
|
/* wait for the BLT engine to stop being busy */ |
|
do { |
|
i = read_gp(par, GP_BLT_STATUS); |
|
} while ((i & GP_BLT_STATUS_PB) || !(i & GP_BLT_STATUS_CE)); |
|
|
|
/* save MSRs */ |
|
rdmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); |
|
rdmsrl(MSR_GLCP_DOTPLL, par->msr.dotpll); |
|
rdmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); |
|
rdmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); |
|
|
|
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); |
|
|
|
/* save registers */ |
|
memcpy(par->gp, par->gp_regs, sizeof(par->gp)); |
|
memcpy(par->dc, par->dc_regs, sizeof(par->dc)); |
|
memcpy(par->vp, par->vp_regs, sizeof(par->vp)); |
|
memcpy(par->fp, par->vp_regs + VP_FP_START, sizeof(par->fp)); |
|
|
|
/* save the display controller palette */ |
|
write_dc(par, DC_PAL_ADDRESS, 0); |
|
for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++) |
|
par->dc_pal[i] = read_dc(par, DC_PAL_DATA); |
|
|
|
/* save the video processor palette */ |
|
write_vp(par, VP_PAR, 0); |
|
for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++) |
|
par->vp_pal[i] = read_vp(par, VP_PDR); |
|
|
|
/* save the horizontal filter coefficients */ |
|
filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL; |
|
for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) { |
|
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); |
|
par->hcoeff[i] = read_dc(par, DC_FILT_COEFF1); |
|
par->hcoeff[i + 1] = read_dc(par, DC_FILT_COEFF2); |
|
} |
|
|
|
/* save the vertical filter coefficients */ |
|
filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL; |
|
for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) { |
|
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); |
|
par->vcoeff[i] = read_dc(par, DC_FILT_COEFF1); |
|
} |
|
|
|
/* save video coeff ram */ |
|
memcpy(par->vp_coeff, par->vp_regs + VP_VCR, sizeof(par->vp_coeff)); |
|
} |
|
|
|
static void lx_restore_gfx_proc(struct lxfb_par *par) |
|
{ |
|
int i; |
|
|
|
/* a bunch of registers require GP_RASTER_MODE to be set first */ |
|
write_gp(par, GP_RASTER_MODE, par->gp[GP_RASTER_MODE]); |
|
|
|
for (i = 0; i < ARRAY_SIZE(par->gp); i++) { |
|
switch (i) { |
|
case GP_RASTER_MODE: |
|
case GP_VECTOR_MODE: |
|
case GP_BLT_MODE: |
|
case GP_BLT_STATUS: |
|
case GP_HST_SRC: |
|
/* FIXME: restore LUT data */ |
|
case GP_LUT_INDEX: |
|
case GP_LUT_DATA: |
|
/* don't restore these registers */ |
|
break; |
|
|
|
default: |
|
write_gp(par, i, par->gp[i]); |
|
} |
|
} |
|
} |
|
|
|
static void lx_restore_display_ctlr(struct lxfb_par *par) |
|
{ |
|
uint32_t filt; |
|
int i; |
|
|
|
wrmsrl(MSR_LX_SPARE_MSR, par->msr.dcspare); |
|
|
|
for (i = 0; i < ARRAY_SIZE(par->dc); i++) { |
|
switch (i) { |
|
case DC_UNLOCK: |
|
/* unlock the DC; runs first */ |
|
write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK); |
|
break; |
|
|
|
case DC_GENERAL_CFG: |
|
case DC_DISPLAY_CFG: |
|
/* disable all while restoring */ |
|
write_dc(par, i, 0); |
|
break; |
|
|
|
case DC_DV_CTL: |
|
/* set all ram to dirty */ |
|
write_dc(par, i, par->dc[i] | DC_DV_CTL_CLEAR_DV_RAM); |
|
break; |
|
|
|
case DC_RSVD_1: |
|
case DC_RSVD_2: |
|
case DC_RSVD_3: |
|
case DC_LINE_CNT: |
|
case DC_PAL_ADDRESS: |
|
case DC_PAL_DATA: |
|
case DC_DFIFO_DIAG: |
|
case DC_CFIFO_DIAG: |
|
case DC_FILT_COEFF1: |
|
case DC_FILT_COEFF2: |
|
case DC_RSVD_4: |
|
case DC_RSVD_5: |
|
/* don't restore these registers */ |
|
break; |
|
|
|
default: |
|
write_dc(par, i, par->dc[i]); |
|
} |
|
} |
|
|
|
/* restore the palette */ |
|
write_dc(par, DC_PAL_ADDRESS, 0); |
|
for (i = 0; i < ARRAY_SIZE(par->dc_pal); i++) |
|
write_dc(par, DC_PAL_DATA, par->dc_pal[i]); |
|
|
|
/* restore the horizontal filter coefficients */ |
|
filt = par->dc[DC_IRQ_FILT_CTL] | DC_IRQ_FILT_CTL_H_FILT_SEL; |
|
for (i = 0; i < ARRAY_SIZE(par->hcoeff); i += 2) { |
|
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); |
|
write_dc(par, DC_FILT_COEFF1, par->hcoeff[i]); |
|
write_dc(par, DC_FILT_COEFF2, par->hcoeff[i + 1]); |
|
} |
|
|
|
/* restore the vertical filter coefficients */ |
|
filt &= ~DC_IRQ_FILT_CTL_H_FILT_SEL; |
|
for (i = 0; i < ARRAY_SIZE(par->vcoeff); i++) { |
|
write_dc(par, DC_IRQ_FILT_CTL, (filt & 0xffffff00) | i); |
|
write_dc(par, DC_FILT_COEFF1, par->vcoeff[i]); |
|
} |
|
} |
|
|
|
static void lx_restore_video_proc(struct lxfb_par *par) |
|
{ |
|
int i; |
|
|
|
wrmsrl(MSR_LX_GLD_MSR_CONFIG, par->msr.dfglcfg); |
|
wrmsrl(MSR_LX_MSR_PADSEL, par->msr.padsel); |
|
|
|
for (i = 0; i < ARRAY_SIZE(par->vp); i++) { |
|
switch (i) { |
|
case VP_VCFG: |
|
case VP_DCFG: |
|
case VP_PAR: |
|
case VP_PDR: |
|
case VP_CCS: |
|
case VP_RSVD_0: |
|
/* case VP_VDC: */ /* why should this not be restored? */ |
|
case VP_RSVD_1: |
|
case VP_CRC32: |
|
/* don't restore these registers */ |
|
break; |
|
|
|
default: |
|
write_vp(par, i, par->vp[i]); |
|
} |
|
} |
|
|
|
/* restore video processor palette */ |
|
write_vp(par, VP_PAR, 0); |
|
for (i = 0; i < ARRAY_SIZE(par->vp_pal); i++) |
|
write_vp(par, VP_PDR, par->vp_pal[i]); |
|
|
|
/* restore video coeff ram */ |
|
memcpy(par->vp_regs + VP_VCR, par->vp_coeff, sizeof(par->vp_coeff)); |
|
} |
|
|
|
static void lx_restore_regs(struct lxfb_par *par) |
|
{ |
|
int i; |
|
|
|
lx_set_dotpll((u32) (par->msr.dotpll >> 32)); |
|
lx_restore_gfx_proc(par); |
|
lx_restore_display_ctlr(par); |
|
lx_restore_video_proc(par); |
|
|
|
/* Flat Panel */ |
|
for (i = 0; i < ARRAY_SIZE(par->fp); i++) { |
|
switch (i) { |
|
case FP_PM: |
|
case FP_RSVD_0: |
|
case FP_RSVD_1: |
|
case FP_RSVD_2: |
|
case FP_RSVD_3: |
|
case FP_RSVD_4: |
|
/* don't restore these registers */ |
|
break; |
|
|
|
default: |
|
write_fp(par, i, par->fp[i]); |
|
} |
|
} |
|
|
|
/* control the panel */ |
|
if (par->fp[FP_PM] & FP_PM_P) { |
|
/* power on the panel if not already power{ed,ing} on */ |
|
if (!(read_fp(par, FP_PM) & |
|
(FP_PM_PANEL_ON|FP_PM_PANEL_PWR_UP))) |
|
write_fp(par, FP_PM, par->fp[FP_PM]); |
|
} else { |
|
/* power down the panel if not already power{ed,ing} down */ |
|
if (!(read_fp(par, FP_PM) & |
|
(FP_PM_PANEL_OFF|FP_PM_PANEL_PWR_DOWN))) |
|
write_fp(par, FP_PM, par->fp[FP_PM]); |
|
} |
|
|
|
/* turn everything on */ |
|
write_vp(par, VP_VCFG, par->vp[VP_VCFG]); |
|
write_vp(par, VP_DCFG, par->vp[VP_DCFG]); |
|
write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]); |
|
/* do this last; it will enable the FIFO load */ |
|
write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG]); |
|
|
|
/* lock the door behind us */ |
|
write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK); |
|
} |
|
|
|
int lx_powerdown(struct fb_info *info) |
|
{ |
|
struct lxfb_par *par = info->par; |
|
|
|
if (par->powered_down) |
|
return 0; |
|
|
|
lx_save_regs(par); |
|
lx_graphics_disable(info); |
|
|
|
par->powered_down = 1; |
|
return 0; |
|
} |
|
|
|
int lx_powerup(struct fb_info *info) |
|
{ |
|
struct lxfb_par *par = info->par; |
|
|
|
if (!par->powered_down) |
|
return 0; |
|
|
|
lx_restore_regs(par); |
|
|
|
par->powered_down = 0; |
|
return 0; |
|
}
|
|
|