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317 lines
9.7 KiB
317 lines
9.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2011 Marvell International Ltd. All rights reserved. |
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*/ |
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#ifndef __MV_U3D_H |
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#define __MV_U3D_H |
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#define MV_U3D_EP_CONTEXT_ALIGNMENT 32 |
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#define MV_U3D_TRB_ALIGNMENT 16 |
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#define MV_U3D_DMA_BOUNDARY 4096 |
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#define MV_U3D_EP0_MAX_PKT_SIZE 512 |
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/* ep0 transfer state */ |
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#define MV_U3D_WAIT_FOR_SETUP 0 |
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#define MV_U3D_DATA_STATE_XMIT 1 |
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#define MV_U3D_DATA_STATE_NEED_ZLP 2 |
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#define MV_U3D_WAIT_FOR_OUT_STATUS 3 |
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#define MV_U3D_DATA_STATE_RECV 4 |
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#define MV_U3D_STATUS_STAGE 5 |
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#define MV_U3D_EP_MAX_LENGTH_TRANSFER 0x10000 |
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/* USB3 Interrupt Status */ |
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#define MV_U3D_USBINT_SETUP 0x00000001 |
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#define MV_U3D_USBINT_RX_COMPLETE 0x00000002 |
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#define MV_U3D_USBINT_TX_COMPLETE 0x00000004 |
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#define MV_U3D_USBINT_UNDER_RUN 0x00000008 |
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#define MV_U3D_USBINT_RXDESC_ERR 0x00000010 |
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#define MV_U3D_USBINT_TXDESC_ERR 0x00000020 |
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#define MV_U3D_USBINT_RX_TRB_COMPLETE 0x00000040 |
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#define MV_U3D_USBINT_TX_TRB_COMPLETE 0x00000080 |
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#define MV_U3D_USBINT_VBUS_VALID 0x00010000 |
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#define MV_U3D_USBINT_STORAGE_CMD_FULL 0x00020000 |
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#define MV_U3D_USBINT_LINK_CHG 0x01000000 |
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/* USB3 Interrupt Enable */ |
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#define MV_U3D_INTR_ENABLE_SETUP 0x00000001 |
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#define MV_U3D_INTR_ENABLE_RX_COMPLETE 0x00000002 |
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#define MV_U3D_INTR_ENABLE_TX_COMPLETE 0x00000004 |
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#define MV_U3D_INTR_ENABLE_UNDER_RUN 0x00000008 |
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#define MV_U3D_INTR_ENABLE_RXDESC_ERR 0x00000010 |
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#define MV_U3D_INTR_ENABLE_TXDESC_ERR 0x00000020 |
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#define MV_U3D_INTR_ENABLE_RX_TRB_COMPLETE 0x00000040 |
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#define MV_U3D_INTR_ENABLE_TX_TRB_COMPLETE 0x00000080 |
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#define MV_U3D_INTR_ENABLE_RX_BUFFER_ERR 0x00000100 |
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#define MV_U3D_INTR_ENABLE_VBUS_VALID 0x00010000 |
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#define MV_U3D_INTR_ENABLE_STORAGE_CMD_FULL 0x00020000 |
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#define MV_U3D_INTR_ENABLE_LINK_CHG 0x01000000 |
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#define MV_U3D_INTR_ENABLE_PRIME_STATUS 0x02000000 |
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/* USB3 Link Change */ |
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#define MV_U3D_LINK_CHANGE_LINK_UP 0x00000001 |
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#define MV_U3D_LINK_CHANGE_SUSPEND 0x00000002 |
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#define MV_U3D_LINK_CHANGE_RESUME 0x00000004 |
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#define MV_U3D_LINK_CHANGE_WRESET 0x00000008 |
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#define MV_U3D_LINK_CHANGE_HRESET 0x00000010 |
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#define MV_U3D_LINK_CHANGE_VBUS_INVALID 0x00000020 |
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#define MV_U3D_LINK_CHANGE_INACT 0x00000040 |
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#define MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0 0x00000080 |
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#define MV_U3D_LINK_CHANGE_U1 0x00000100 |
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#define MV_U3D_LINK_CHANGE_U2 0x00000200 |
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#define MV_U3D_LINK_CHANGE_U3 0x00000400 |
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/* bridge setting */ |
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#define MV_U3D_BRIDGE_SETTING_VBUS_VALID (1 << 16) |
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/* Command Register Bit Masks */ |
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#define MV_U3D_CMD_RUN_STOP 0x00000001 |
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#define MV_U3D_CMD_CTRL_RESET 0x00000002 |
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/* ep control register */ |
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#define MV_U3D_EPXCR_EP_TYPE_CONTROL 0 |
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#define MV_U3D_EPXCR_EP_TYPE_ISOC 1 |
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#define MV_U3D_EPXCR_EP_TYPE_BULK 2 |
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#define MV_U3D_EPXCR_EP_TYPE_INT 3 |
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#define MV_U3D_EPXCR_EP_ENABLE_SHIFT 4 |
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#define MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT 12 |
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#define MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT 16 |
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#define MV_U3D_USB_BULK_BURST_OUT 6 |
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#define MV_U3D_USB_BULK_BURST_IN 14 |
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#define MV_U3D_EPXCR_EP_FLUSH (1 << 7) |
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#define MV_U3D_EPXCR_EP_HALT (1 << 1) |
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#define MV_U3D_EPXCR_EP_INIT (1) |
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/* TX/RX Status Register */ |
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#define MV_U3D_XFERSTATUS_COMPLETE_SHIFT 24 |
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#define MV_U3D_COMPLETE_INVALID 0 |
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#define MV_U3D_COMPLETE_SUCCESS 1 |
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#define MV_U3D_COMPLETE_BUFF_ERR 2 |
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#define MV_U3D_COMPLETE_SHORT_PACKET 3 |
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#define MV_U3D_COMPLETE_TRB_ERR 5 |
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#define MV_U3D_XFERSTATUS_TRB_LENGTH_MASK (0xFFFFFF) |
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#define MV_U3D_USB_LINK_BYPASS_VBUS 0x8 |
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#define MV_U3D_LTSSM_PHY_INIT_DONE 0x80000000 |
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#define MV_U3D_LTSSM_NEVER_GO_COMPLIANCE 0x40000000 |
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#define MV_U3D_USB3_OP_REGS_OFFSET 0x100 |
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#define MV_U3D_USB3_PHY_OFFSET 0xB800 |
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#define DCS_ENABLE 0x1 |
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/* timeout */ |
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#define MV_U3D_RESET_TIMEOUT 10000 |
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#define MV_U3D_FLUSH_TIMEOUT 100000 |
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#define MV_U3D_OWN_TIMEOUT 10000 |
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#define LOOPS_USEC_SHIFT 4 |
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#define LOOPS_USEC (1 << LOOPS_USEC_SHIFT) |
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#define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT) |
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/* ep direction */ |
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#define MV_U3D_EP_DIR_IN 1 |
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#define MV_U3D_EP_DIR_OUT 0 |
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#define mv_u3d_ep_dir(ep) (((ep)->ep_num == 0) ? \ |
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((ep)->u3d->ep0_dir) : ((ep)->direction)) |
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/* usb capability registers */ |
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struct mv_u3d_cap_regs { |
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u32 rsvd[5]; |
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u32 dboff; /* doorbell register offset */ |
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u32 rtsoff; /* runtime register offset */ |
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u32 vuoff; /* vendor unique register offset */ |
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}; |
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/* operation registers */ |
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struct mv_u3d_op_regs { |
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u32 usbcmd; /* Command register */ |
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u32 rsvd1[11]; |
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u32 dcbaapl; /* Device Context Base Address low register */ |
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u32 dcbaaph; /* Device Context Base Address high register */ |
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u32 rsvd2[243]; |
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u32 portsc; /* port status and control register*/ |
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u32 portlinkinfo; /* port link info register*/ |
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u32 rsvd3[9917]; |
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u32 doorbell; /* doorbell register */ |
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}; |
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/* control endpoint enable registers */ |
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struct epxcr { |
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u32 epxoutcr0; /* ep out control 0 register */ |
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u32 epxoutcr1; /* ep out control 1 register */ |
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u32 epxincr0; /* ep in control 0 register */ |
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u32 epxincr1; /* ep in control 1 register */ |
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}; |
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/* transfer status registers */ |
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struct xferstatus { |
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u32 curdeqlo; /* current TRB pointer low */ |
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u32 curdeqhi; /* current TRB pointer high */ |
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u32 statuslo; /* transfer status low */ |
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u32 statushi; /* transfer status high */ |
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}; |
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/* vendor unique control registers */ |
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struct mv_u3d_vuc_regs { |
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u32 ctrlepenable; /* control endpoint enable register */ |
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u32 setuplock; /* setup lock register */ |
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u32 endcomplete; /* endpoint transfer complete register */ |
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u32 intrcause; /* interrupt cause register */ |
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u32 intrenable; /* interrupt enable register */ |
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u32 trbcomplete; /* TRB complete register */ |
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u32 linkchange; /* link change register */ |
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u32 rsvd1[5]; |
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u32 trbunderrun; /* TRB underrun register */ |
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u32 rsvd2[43]; |
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u32 bridgesetting; /* bridge setting register */ |
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u32 rsvd3[7]; |
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struct xferstatus txst[16]; /* TX status register */ |
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struct xferstatus rxst[16]; /* RX status register */ |
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u32 ltssm; /* LTSSM control register */ |
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u32 pipe; /* PIPE control register */ |
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u32 linkcr0; /* link control 0 register */ |
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u32 linkcr1; /* link control 1 register */ |
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u32 rsvd6[60]; |
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u32 mib0; /* MIB0 counter register */ |
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u32 usblink; /* usb link control register */ |
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u32 ltssmstate; /* LTSSM state register */ |
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u32 linkerrorcause; /* link error cause register */ |
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u32 rsvd7[60]; |
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u32 devaddrtiebrkr; /* device address and tie breaker */ |
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u32 itpinfo0; /* ITP info 0 register */ |
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u32 itpinfo1; /* ITP info 1 register */ |
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u32 rsvd8[61]; |
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struct epxcr epcr[16]; /* ep control register */ |
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u32 rsvd9[64]; |
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u32 phyaddr; /* PHY address register */ |
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u32 phydata; /* PHY data register */ |
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}; |
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/* Endpoint context structure */ |
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struct mv_u3d_ep_context { |
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u32 rsvd0; |
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u32 rsvd1; |
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u32 trb_addr_lo; /* TRB address low 32 bit */ |
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u32 trb_addr_hi; /* TRB address high 32 bit */ |
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u32 rsvd2; |
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u32 rsvd3; |
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struct usb_ctrlrequest setup_buffer; /* setup data buffer */ |
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}; |
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/* TRB control data structure */ |
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struct mv_u3d_trb_ctrl { |
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u32 own:1; /* owner of TRB */ |
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u32 rsvd1:3; |
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u32 chain:1; /* associate this TRB with the |
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next TRB on the Ring */ |
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u32 ioc:1; /* interrupt on complete */ |
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u32 rsvd2:4; |
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u32 type:6; /* TRB type */ |
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#define TYPE_NORMAL 1 |
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#define TYPE_DATA 3 |
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#define TYPE_LINK 6 |
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u32 dir:1; /* Working at data stage of control endpoint |
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operation. 0 is OUT and 1 is IN. */ |
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u32 rsvd3:15; |
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}; |
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/* TRB data structure |
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* For multiple TRB, all the TRBs' physical address should be continuous. |
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*/ |
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struct mv_u3d_trb_hw { |
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u32 buf_addr_lo; /* data buffer address low 32 bit */ |
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u32 buf_addr_hi; /* data buffer address high 32 bit */ |
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u32 trb_len; /* transfer length */ |
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struct mv_u3d_trb_ctrl ctrl; /* TRB control data */ |
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}; |
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/* TRB structure */ |
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struct mv_u3d_trb { |
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struct mv_u3d_trb_hw *trb_hw; /* point to the trb_hw structure */ |
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dma_addr_t trb_dma; /* dma address for this trb_hw */ |
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struct list_head trb_list; /* trb list */ |
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}; |
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/* device data structure */ |
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struct mv_u3d { |
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struct usb_gadget gadget; |
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struct usb_gadget_driver *driver; |
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spinlock_t lock; /* device lock */ |
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struct completion *done; |
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struct device *dev; |
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int irq; |
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/* usb controller registers */ |
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struct mv_u3d_cap_regs __iomem *cap_regs; |
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struct mv_u3d_op_regs __iomem *op_regs; |
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struct mv_u3d_vuc_regs __iomem *vuc_regs; |
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void __iomem *phy_regs; |
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unsigned int max_eps; |
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struct mv_u3d_ep_context *ep_context; |
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size_t ep_context_size; |
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dma_addr_t ep_context_dma; |
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struct dma_pool *trb_pool; /* for TRB data structure */ |
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struct mv_u3d_ep *eps; |
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struct mv_u3d_req *status_req; /* ep0 status request */ |
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struct usb_ctrlrequest local_setup_buff; /* store setup data*/ |
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unsigned int resume_state; /* USB state to resume */ |
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unsigned int usb_state; /* USB current state */ |
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unsigned int ep0_state; /* Endpoint zero state */ |
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unsigned int ep0_dir; |
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unsigned int dev_addr; /* device address */ |
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unsigned int errors; |
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unsigned softconnect:1; |
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unsigned vbus_active:1; /* vbus is active or not */ |
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unsigned remote_wakeup:1; /* support remote wakeup */ |
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unsigned clock_gating:1; /* clock gating or not */ |
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unsigned active:1; /* udc is active or not */ |
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unsigned vbus_valid_detect:1; /* udc vbus detection */ |
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struct mv_usb_addon_irq *vbus; |
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unsigned int power; |
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struct clk *clk; |
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}; |
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/* endpoint data structure */ |
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struct mv_u3d_ep { |
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struct usb_ep ep; |
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struct mv_u3d *u3d; |
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struct list_head queue; /* ep request queued hardware */ |
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struct list_head req_list; /* list of ep request */ |
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struct mv_u3d_ep_context *ep_context; /* ep context */ |
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u32 direction; |
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char name[14]; |
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u32 processing; /* there is ep request |
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queued on haredware */ |
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spinlock_t req_lock; /* ep lock */ |
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unsigned wedge:1; |
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unsigned enabled:1; |
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unsigned ep_type:2; |
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unsigned ep_num:8; |
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}; |
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/* request data structure */ |
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struct mv_u3d_req { |
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struct usb_request req; |
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struct mv_u3d_ep *ep; |
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struct list_head queue; /* ep requst queued on hardware */ |
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struct list_head list; /* ep request list */ |
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struct list_head trb_list; /* trb list of a request */ |
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struct mv_u3d_trb *trb_head; /* point to first trb of a request */ |
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unsigned trb_count; /* TRB number in the chain */ |
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unsigned chain; /* TRB chain or not */ |
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}; |
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#endif
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