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118 lines
4.7 KiB
118 lines
4.7 KiB
/* |
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* This file is provided under a dual BSD/GPLv2 license. When using or |
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* redistributing this file, you may do so under either license. |
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* |
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* GPL LICENSE SUMMARY |
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* |
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* Copyright(c) 2012-2017 Intel Corporation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of version 2 of the GNU General Public License as |
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* published by the Free Software Foundation. |
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* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2012-2017 Intel Corporation. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copy |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name of Intel Corporation nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef _NTB_INTEL_GEN3_H_ |
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#define _NTB_INTEL_GEN3_H_ |
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#include "ntb_hw_intel.h" |
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/* Intel Skylake Xeon hardware */ |
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#define GEN3_IMBAR1SZ_OFFSET 0x00d0 |
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#define GEN3_IMBAR2SZ_OFFSET 0x00d1 |
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#define GEN3_EMBAR1SZ_OFFSET 0x00d2 |
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#define GEN3_EMBAR2SZ_OFFSET 0x00d3 |
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#define GEN3_DEVCTRL_OFFSET 0x0098 |
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#define GEN3_DEVSTS_OFFSET 0x009a |
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#define GEN3_UNCERRSTS_OFFSET 0x014c |
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#define GEN3_CORERRSTS_OFFSET 0x0158 |
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#define GEN3_LINK_STATUS_OFFSET 0x01a2 |
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#define GEN3_NTBCNTL_OFFSET 0x0000 |
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#define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */ |
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#define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */ |
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#define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */ |
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#define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */ |
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#define GEN3_IM_INT_STATUS_OFFSET 0x0040 |
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#define GEN3_IM_INT_DISABLE_OFFSET 0x0048 |
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#define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */ |
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#define GEN3_USMEMMISS_OFFSET 0x0070 |
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#define GEN3_INTVEC_OFFSET 0x00d0 |
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#define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */ |
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#define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */ |
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#define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */ |
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#define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */ |
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#define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */ |
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#define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */ |
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#define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */ |
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#define GEN3_EM_INT_STATUS_OFFSET 0x4040 |
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#define GEN3_EM_INT_DISABLE_OFFSET 0x4048 |
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#define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */ |
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#define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */ |
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#define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */ |
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#define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */ |
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#define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */ |
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#define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */ |
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#define GEN3_DB_COUNT 32 |
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#define GEN3_DB_LINK 32 |
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#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK) |
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#define GEN3_DB_MSIX_VECTOR_COUNT 33 |
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#define GEN3_DB_MSIX_VECTOR_SHIFT 1 |
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#define GEN3_DB_TOTAL_SHIFT 33 |
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#define GEN3_SPAD_COUNT 16 |
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static inline u64 gen3_db_ioread(const void __iomem *mmio) |
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{ |
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return ioread64(mmio); |
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} |
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static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio) |
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{ |
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iowrite64(bits, mmio); |
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} |
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ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf, |
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size_t count, loff_t *offp); |
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int gen3_init_dev(struct intel_ntb_dev *ndev); |
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int intel_ntb3_link_enable(struct ntb_dev *ntb, enum ntb_speed max_speed, |
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enum ntb_width max_width); |
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u64 intel_ntb3_db_read(struct ntb_dev *ntb); |
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int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits); |
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int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits); |
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int intel_ntb3_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr, |
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resource_size_t *db_size, |
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u64 *db_data, int db_bit); |
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extern const struct ntb_dev_ops intel_ntb3_ops; |
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#endif
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