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321 lines
8.2 KiB
321 lines
8.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com/ |
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* |
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* Author: Jacek Anaszewski <[email protected]> |
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* |
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* Register interface file for JPEG driver on Exynos4x12. |
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*/ |
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#include <linux/io.h> |
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#include <linux/delay.h> |
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#include "jpeg-core.h" |
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#include "jpeg-hw-exynos4.h" |
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#include "jpeg-regs.h" |
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void exynos4_jpeg_sw_reset(void __iomem *base) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_JPEG_CNTL_REG); |
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writel(reg & ~(EXYNOS4_DEC_MODE | EXYNOS4_ENC_MODE), |
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base + EXYNOS4_JPEG_CNTL_REG); |
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reg = readl(base + EXYNOS4_JPEG_CNTL_REG); |
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writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); |
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udelay(100); |
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writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); |
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} |
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void exynos4_jpeg_set_enc_dec_mode(void __iomem *base, unsigned int mode) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_JPEG_CNTL_REG); |
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/* set exynos4_jpeg mod register */ |
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if (mode == S5P_JPEG_DECODE) { |
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writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | |
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EXYNOS4_DEC_MODE, |
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base + EXYNOS4_JPEG_CNTL_REG); |
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} else if (mode == S5P_JPEG_ENCODE) {/* encode */ |
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writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | |
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EXYNOS4_ENC_MODE, |
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base + EXYNOS4_JPEG_CNTL_REG); |
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} else { /* disable both */ |
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writel(reg & EXYNOS4_ENC_DEC_MODE_MASK, |
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base + EXYNOS4_JPEG_CNTL_REG); |
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} |
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} |
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void __exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt, |
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unsigned int version) |
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{ |
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unsigned int reg; |
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unsigned int exynos4_swap_chroma_cbcr; |
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unsigned int exynos4_swap_chroma_crcb; |
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if (version == SJPEG_EXYNOS4) { |
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exynos4_swap_chroma_cbcr = EXYNOS4_SWAP_CHROMA_CBCR; |
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exynos4_swap_chroma_crcb = EXYNOS4_SWAP_CHROMA_CRCB; |
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} else { |
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exynos4_swap_chroma_cbcr = EXYNOS5433_SWAP_CHROMA_CBCR; |
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exynos4_swap_chroma_crcb = EXYNOS5433_SWAP_CHROMA_CRCB; |
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} |
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reg = readl(base + EXYNOS4_IMG_FMT_REG) & |
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EXYNOS4_ENC_IN_FMT_MASK; /* clear except enc format */ |
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switch (img_fmt) { |
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case V4L2_PIX_FMT_GREY: |
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reg = reg | EXYNOS4_ENC_GRAY_IMG | EXYNOS4_GRAY_IMG_IP; |
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break; |
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case V4L2_PIX_FMT_RGB32: |
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reg = reg | EXYNOS4_ENC_RGB_IMG | |
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EXYNOS4_RGB_IP_RGB_32BIT_IMG; |
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break; |
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case V4L2_PIX_FMT_RGB565: |
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reg = reg | EXYNOS4_ENC_RGB_IMG | |
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EXYNOS4_RGB_IP_RGB_16BIT_IMG; |
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break; |
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case V4L2_PIX_FMT_NV24: |
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reg = reg | EXYNOS4_ENC_YUV_444_IMG | |
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EXYNOS4_YUV_444_IP_YUV_444_2P_IMG | |
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exynos4_swap_chroma_cbcr; |
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break; |
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case V4L2_PIX_FMT_NV42: |
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reg = reg | EXYNOS4_ENC_YUV_444_IMG | |
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EXYNOS4_YUV_444_IP_YUV_444_2P_IMG | |
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exynos4_swap_chroma_crcb; |
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break; |
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case V4L2_PIX_FMT_YUYV: |
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reg = reg | EXYNOS4_DEC_YUV_422_IMG | |
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EXYNOS4_YUV_422_IP_YUV_422_1P_IMG | |
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exynos4_swap_chroma_cbcr; |
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break; |
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case V4L2_PIX_FMT_YVYU: |
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reg = reg | EXYNOS4_DEC_YUV_422_IMG | |
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EXYNOS4_YUV_422_IP_YUV_422_1P_IMG | |
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exynos4_swap_chroma_crcb; |
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break; |
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case V4L2_PIX_FMT_NV16: |
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reg = reg | EXYNOS4_DEC_YUV_422_IMG | |
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EXYNOS4_YUV_422_IP_YUV_422_2P_IMG | |
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exynos4_swap_chroma_cbcr; |
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break; |
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case V4L2_PIX_FMT_NV61: |
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reg = reg | EXYNOS4_DEC_YUV_422_IMG | |
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EXYNOS4_YUV_422_IP_YUV_422_2P_IMG | |
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exynos4_swap_chroma_crcb; |
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break; |
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case V4L2_PIX_FMT_NV12: |
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reg = reg | EXYNOS4_DEC_YUV_420_IMG | |
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EXYNOS4_YUV_420_IP_YUV_420_2P_IMG | |
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exynos4_swap_chroma_cbcr; |
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break; |
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case V4L2_PIX_FMT_NV21: |
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reg = reg | EXYNOS4_DEC_YUV_420_IMG | |
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EXYNOS4_YUV_420_IP_YUV_420_2P_IMG | |
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exynos4_swap_chroma_crcb; |
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break; |
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case V4L2_PIX_FMT_YUV420: |
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reg = reg | EXYNOS4_DEC_YUV_420_IMG | |
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EXYNOS4_YUV_420_IP_YUV_420_3P_IMG | |
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exynos4_swap_chroma_cbcr; |
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break; |
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default: |
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break; |
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} |
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writel(reg, base + EXYNOS4_IMG_FMT_REG); |
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} |
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void __exynos4_jpeg_set_enc_out_fmt(void __iomem *base, unsigned int out_fmt, |
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unsigned int version) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_IMG_FMT_REG) & |
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~(version == SJPEG_EXYNOS4 ? EXYNOS4_ENC_FMT_MASK : |
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EXYNOS5433_ENC_FMT_MASK); /* clear enc format */ |
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switch (out_fmt) { |
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case V4L2_JPEG_CHROMA_SUBSAMPLING_GRAY: |
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reg = reg | EXYNOS4_ENC_FMT_GRAY; |
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break; |
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case V4L2_JPEG_CHROMA_SUBSAMPLING_444: |
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reg = reg | EXYNOS4_ENC_FMT_YUV_444; |
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break; |
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case V4L2_JPEG_CHROMA_SUBSAMPLING_422: |
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reg = reg | EXYNOS4_ENC_FMT_YUV_422; |
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break; |
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case V4L2_JPEG_CHROMA_SUBSAMPLING_420: |
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reg = reg | EXYNOS4_ENC_FMT_YUV_420; |
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break; |
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default: |
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break; |
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} |
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writel(reg, base + EXYNOS4_IMG_FMT_REG); |
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} |
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void exynos4_jpeg_set_interrupt(void __iomem *base, unsigned int version) |
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{ |
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unsigned int reg; |
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if (version == SJPEG_EXYNOS4) { |
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reg = readl(base + EXYNOS4_INT_EN_REG) & ~EXYNOS4_INT_EN_MASK; |
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writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); |
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} else { |
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reg = readl(base + EXYNOS4_INT_EN_REG) & |
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~EXYNOS5433_INT_EN_MASK; |
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writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); |
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} |
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} |
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unsigned int exynos4_jpeg_get_int_status(void __iomem *base) |
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{ |
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return readl(base + EXYNOS4_INT_STATUS_REG); |
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} |
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unsigned int exynos4_jpeg_get_fifo_status(void __iomem *base) |
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{ |
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return readl(base + EXYNOS4_FIFO_STATUS_REG); |
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} |
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void exynos4_jpeg_set_huf_table_enable(void __iomem *base, int value) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~EXYNOS4_HUF_TBL_EN; |
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if (value == 1) |
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writel(reg | EXYNOS4_HUF_TBL_EN, |
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base + EXYNOS4_JPEG_CNTL_REG); |
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else |
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writel(reg & ~EXYNOS4_HUF_TBL_EN, |
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base + EXYNOS4_JPEG_CNTL_REG); |
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} |
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void exynos4_jpeg_set_sys_int_enable(void __iomem *base, int value) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_JPEG_CNTL_REG) & ~(EXYNOS4_SYS_INT_EN); |
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if (value == 1) |
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writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); |
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else |
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writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); |
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} |
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void exynos4_jpeg_set_stream_buf_address(void __iomem *base, |
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unsigned int address) |
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{ |
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writel(address, base + EXYNOS4_OUT_MEM_BASE_REG); |
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} |
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void exynos4_jpeg_set_stream_size(void __iomem *base, |
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unsigned int x_value, unsigned int y_value) |
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{ |
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writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */ |
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writel(EXYNOS4_X_SIZE(x_value) | EXYNOS4_Y_SIZE(y_value), |
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base + EXYNOS4_JPEG_IMG_SIZE_REG); |
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} |
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void exynos4_jpeg_set_frame_buf_address(void __iomem *base, |
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struct s5p_jpeg_addr *exynos4_jpeg_addr) |
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{ |
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writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG); |
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writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG); |
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writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG); |
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} |
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void exynos4_jpeg_set_encode_tbl_select(void __iomem *base, |
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enum exynos4_jpeg_img_quality_level level) |
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{ |
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unsigned int reg; |
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reg = EXYNOS4_Q_TBL_COMP1_0 | EXYNOS4_Q_TBL_COMP2_1 | |
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EXYNOS4_Q_TBL_COMP3_1 | |
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EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 | |
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EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 | |
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EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1; |
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writel(reg, base + EXYNOS4_TBL_SEL_REG); |
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} |
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void exynos4_jpeg_set_dec_components(void __iomem *base, int n) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_TBL_SEL_REG); |
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reg |= EXYNOS4_NF(n); |
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writel(reg, base + EXYNOS4_TBL_SEL_REG); |
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} |
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void exynos4_jpeg_select_dec_q_tbl(void __iomem *base, char c, char x) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_TBL_SEL_REG); |
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reg |= EXYNOS4_Q_TBL_COMP(c, x); |
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writel(reg, base + EXYNOS4_TBL_SEL_REG); |
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} |
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void exynos4_jpeg_select_dec_h_tbl(void __iomem *base, char c, char x) |
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{ |
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unsigned int reg; |
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reg = readl(base + EXYNOS4_TBL_SEL_REG); |
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reg |= EXYNOS4_HUFF_TBL_COMP(c, x); |
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writel(reg, base + EXYNOS4_TBL_SEL_REG); |
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} |
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void exynos4_jpeg_set_encode_hoff_cnt(void __iomem *base, unsigned int fmt) |
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{ |
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if (fmt == V4L2_PIX_FMT_GREY) |
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writel(0xd2, base + EXYNOS4_HUFF_CNT_REG); |
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else |
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writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG); |
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} |
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unsigned int exynos4_jpeg_get_stream_size(void __iomem *base) |
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{ |
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return readl(base + EXYNOS4_BITSTREAM_SIZE_REG); |
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} |
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void exynos4_jpeg_set_dec_bitstream_size(void __iomem *base, unsigned int size) |
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{ |
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writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG); |
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} |
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void exynos4_jpeg_get_frame_size(void __iomem *base, |
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unsigned int *width, unsigned int *height) |
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{ |
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*width = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) & |
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EXYNOS4_DECODED_SIZE_MASK); |
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*height = (readl(base + EXYNOS4_DECODE_XY_SIZE_REG) >> 16) & |
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EXYNOS4_DECODED_SIZE_MASK; |
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} |
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unsigned int exynos4_jpeg_get_frame_fmt(void __iomem *base) |
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{ |
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return readl(base + EXYNOS4_DECODE_IMG_FMT_REG) & |
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EXYNOS4_JPEG_DECODED_IMG_FMT_MASK; |
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} |
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void exynos4_jpeg_set_timer_count(void __iomem *base, unsigned int size) |
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{ |
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writel(size, base + EXYNOS4_INT_TIMER_COUNT_REG); |
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}
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