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19 KiB
775 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* OmniVision OV96xx Camera Driver |
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* |
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* Copyright (C) 2009 Marek Vasut <[email protected]> |
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* |
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* Based on ov772x camera driver: |
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* |
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* Copyright (C) 2008 Renesas Solutions Corp. |
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* Kuninori Morimoto <[email protected]> |
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* |
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* Based on ov7670 and soc_camera_platform driver, |
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* transition from soc_camera to pxa_camera based on mt9m111 |
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* |
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* Copyright 2006-7 Jonathan Corbet <[email protected]> |
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* Copyright (C) 2008 Magnus Damm |
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* Copyright (C) 2008, Guennadi Liakhovetski <[email protected]> |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/i2c.h> |
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#include <linux/slab.h> |
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#include <linux/delay.h> |
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#include <linux/v4l2-mediabus.h> |
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#include <linux/videodev2.h> |
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#include <media/v4l2-async.h> |
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#include <media/v4l2-common.h> |
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#include <media/v4l2-ctrls.h> |
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#include <media/v4l2-device.h> |
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#include <media/v4l2-event.h> |
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#include <linux/gpio/consumer.h> |
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#include "ov9640.h" |
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#define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev) |
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|
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/* default register setup */ |
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static const struct ov9640_reg ov9640_regs_dflt[] = { |
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{ OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP }, |
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{ OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS | |
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OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN }, |
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{ OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) }, |
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{ OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD }, |
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{ OV9640_TSLB, OV9640_TSLB_YUYV_UYVY }, |
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{ OV9640_COM16, OV9640_COM16_RB_AVG }, |
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|
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/* Gamma curve P */ |
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{ 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 }, |
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{ 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 }, |
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{ 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 }, |
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{ 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 }, |
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/* Gamma curve T */ |
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{ 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 }, |
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{ 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 }, |
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{ 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e }, |
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{ 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 }, |
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}; |
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|
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/* Configurations |
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* NOTE: for YUV, alter the following registers: |
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* COM12 |= OV9640_COM12_YUV_AVG |
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* |
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* for RGB, alter the following registers: |
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* COM7 |= OV9640_COM7_RGB |
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* COM13 |= OV9640_COM13_RGB_AVG |
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* COM15 |= proper RGB color encoding mode |
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*/ |
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static const struct ov9640_reg ov9640_regs_qqcif[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) }, |
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{ OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP }, |
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{ OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, |
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{ OV9640_COM7, OV9640_COM7_QCIF }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_qqvga[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) }, |
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{ OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP }, |
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{ OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, |
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{ OV9640_COM7, OV9640_COM7_QVGA }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_qcif[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) }, |
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{ OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, |
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{ OV9640_COM7, OV9640_COM7_QCIF }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_qvga[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) }, |
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{ OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD }, |
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{ OV9640_COM7, OV9640_COM7_QVGA }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_cif[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) }, |
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{ OV9640_COM3, OV9640_COM3_VP }, |
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{ OV9640_COM7, OV9640_COM7_CIF }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_vga[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) }, |
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{ OV9640_COM3, OV9640_COM3_VP }, |
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{ OV9640_COM7, OV9640_COM7_VGA }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_sxga[] = { |
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{ OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) }, |
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{ OV9640_COM3, OV9640_COM3_VP }, |
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{ OV9640_COM7, 0 }, |
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{ OV9640_COM12, OV9640_COM12_RSVD }, |
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{ OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN }, |
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{ OV9640_COM15, OV9640_COM15_OR_10F0 }, |
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}; |
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static const struct ov9640_reg ov9640_regs_yuv[] = { |
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{ OV9640_MTX1, 0x58 }, |
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{ OV9640_MTX2, 0x48 }, |
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{ OV9640_MTX3, 0x10 }, |
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{ OV9640_MTX4, 0x28 }, |
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{ OV9640_MTX5, 0x48 }, |
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{ OV9640_MTX6, 0x70 }, |
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{ OV9640_MTX7, 0x40 }, |
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{ OV9640_MTX8, 0x40 }, |
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{ OV9640_MTX9, 0x40 }, |
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{ OV9640_MTXS, 0x0f }, |
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}; |
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static const struct ov9640_reg ov9640_regs_rgb[] = { |
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{ OV9640_MTX1, 0x71 }, |
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{ OV9640_MTX2, 0x3e }, |
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{ OV9640_MTX3, 0x0c }, |
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{ OV9640_MTX4, 0x33 }, |
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{ OV9640_MTX5, 0x72 }, |
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{ OV9640_MTX6, 0x00 }, |
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{ OV9640_MTX7, 0x2b }, |
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{ OV9640_MTX8, 0x66 }, |
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{ OV9640_MTX9, 0xd2 }, |
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{ OV9640_MTXS, 0x65 }, |
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}; |
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static const u32 ov9640_codes[] = { |
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MEDIA_BUS_FMT_UYVY8_2X8, |
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MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE, |
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MEDIA_BUS_FMT_RGB565_2X8_LE, |
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}; |
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/* read a register */ |
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static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val) |
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{ |
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int ret; |
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u8 data = reg; |
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struct i2c_msg msg = { |
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.addr = client->addr, |
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.flags = 0, |
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.len = 1, |
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.buf = &data, |
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}; |
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ret = i2c_transfer(client->adapter, &msg, 1); |
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if (ret < 0) |
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goto err; |
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msg.flags = I2C_M_RD; |
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ret = i2c_transfer(client->adapter, &msg, 1); |
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if (ret < 0) |
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goto err; |
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*val = data; |
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return 0; |
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err: |
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dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); |
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return ret; |
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} |
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/* write a register */ |
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static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val) |
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{ |
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int ret; |
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u8 _val; |
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unsigned char data[2] = { reg, val }; |
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struct i2c_msg msg = { |
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.addr = client->addr, |
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.flags = 0, |
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.len = 2, |
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.buf = data, |
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}; |
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ret = i2c_transfer(client->adapter, &msg, 1); |
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if (ret < 0) { |
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dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); |
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return ret; |
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} |
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/* we have to read the register back ... no idea why, maybe HW bug */ |
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ret = ov9640_reg_read(client, reg, &_val); |
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if (ret) |
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dev_err(&client->dev, |
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"Failed reading back register 0x%02x!\n", reg); |
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return 0; |
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} |
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/* Read a register, alter its bits, write it back */ |
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static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset) |
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{ |
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u8 val; |
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int ret; |
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ret = ov9640_reg_read(client, reg, &val); |
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if (ret) { |
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dev_err(&client->dev, |
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"[Read]-Modify-Write of register %02x failed!\n", reg); |
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return ret; |
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} |
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val |= set; |
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val &= ~unset; |
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ret = ov9640_reg_write(client, reg, val); |
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if (ret) |
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dev_err(&client->dev, |
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"Read-Modify-[Write] of register %02x failed!\n", reg); |
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return ret; |
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} |
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/* Soft reset the camera. This has nothing to do with the RESET pin! */ |
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static int ov9640_reset(struct i2c_client *client) |
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{ |
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int ret; |
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ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET); |
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if (ret) |
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dev_err(&client->dev, |
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"An error occurred while entering soft reset!\n"); |
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return ret; |
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} |
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/* Start/Stop streaming from the device */ |
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static int ov9640_s_stream(struct v4l2_subdev *sd, int enable) |
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{ |
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return 0; |
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} |
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/* Set status of additional camera capabilities */ |
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static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl) |
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{ |
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struct ov9640_priv *priv = container_of(ctrl->handler, |
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struct ov9640_priv, hdl); |
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struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev); |
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switch (ctrl->id) { |
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case V4L2_CID_VFLIP: |
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if (ctrl->val) |
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return ov9640_reg_rmw(client, OV9640_MVFP, |
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OV9640_MVFP_V, 0); |
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return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V); |
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case V4L2_CID_HFLIP: |
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if (ctrl->val) |
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return ov9640_reg_rmw(client, OV9640_MVFP, |
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OV9640_MVFP_H, 0); |
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return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H); |
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} |
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return -EINVAL; |
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} |
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#ifdef CONFIG_VIDEO_ADV_DEBUG |
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static int ov9640_get_register(struct v4l2_subdev *sd, |
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struct v4l2_dbg_register *reg) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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int ret; |
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u8 val; |
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if (reg->reg & ~0xff) |
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return -EINVAL; |
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reg->size = 1; |
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ret = ov9640_reg_read(client, reg->reg, &val); |
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if (ret) |
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return ret; |
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reg->val = (__u64)val; |
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return 0; |
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} |
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static int ov9640_set_register(struct v4l2_subdev *sd, |
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const struct v4l2_dbg_register *reg) |
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{ |
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struct i2c_client *client = v4l2_get_subdevdata(sd); |
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if (reg->reg & ~0xff || reg->val & ~0xff) |
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return -EINVAL; |
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return ov9640_reg_write(client, reg->reg, reg->val); |
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} |
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#endif |
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static int ov9640_s_power(struct v4l2_subdev *sd, int on) |
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{ |
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struct ov9640_priv *priv = to_ov9640_sensor(sd); |
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int ret = 0; |
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if (on) { |
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gpiod_set_value(priv->gpio_power, 1); |
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usleep_range(1000, 2000); |
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ret = clk_prepare_enable(priv->clk); |
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usleep_range(1000, 2000); |
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gpiod_set_value(priv->gpio_reset, 0); |
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} else { |
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gpiod_set_value(priv->gpio_reset, 1); |
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usleep_range(1000, 2000); |
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clk_disable_unprepare(priv->clk); |
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usleep_range(1000, 2000); |
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gpiod_set_value(priv->gpio_power, 0); |
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} |
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return ret; |
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} |
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/* select nearest higher resolution for capture */ |
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static void ov9640_res_roundup(u32 *width, u32 *height) |
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{ |
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unsigned int i; |
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enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA }; |
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static const u32 res_x[] = { 88, 160, 176, 320, 352, 640, 1280 }; |
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static const u32 res_y[] = { 72, 120, 144, 240, 288, 480, 960 }; |
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for (i = 0; i < ARRAY_SIZE(res_x); i++) { |
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if (res_x[i] >= *width && res_y[i] >= *height) { |
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*width = res_x[i]; |
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*height = res_y[i]; |
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return; |
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} |
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} |
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*width = res_x[SXGA]; |
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*height = res_y[SXGA]; |
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} |
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/* Prepare necessary register changes depending on color encoding */ |
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static void ov9640_alter_regs(u32 code, |
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struct ov9640_reg_alt *alt) |
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{ |
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switch (code) { |
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default: |
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case MEDIA_BUS_FMT_UYVY8_2X8: |
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alt->com12 = OV9640_COM12_YUV_AVG; |
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alt->com13 = OV9640_COM13_Y_DELAY_EN | |
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OV9640_COM13_YUV_DLY(0x01); |
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break; |
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case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: |
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alt->com7 = OV9640_COM7_RGB; |
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alt->com13 = OV9640_COM13_RGB_AVG; |
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alt->com15 = OV9640_COM15_RGB_555; |
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break; |
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case MEDIA_BUS_FMT_RGB565_2X8_LE: |
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alt->com7 = OV9640_COM7_RGB; |
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alt->com13 = OV9640_COM13_RGB_AVG; |
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alt->com15 = OV9640_COM15_RGB_565; |
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break; |
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} |
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} |
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/* Setup registers according to resolution and color encoding */ |
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static int ov9640_write_regs(struct i2c_client *client, u32 width, |
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u32 code, struct ov9640_reg_alt *alts) |
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{ |
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const struct ov9640_reg *ov9640_regs, *matrix_regs; |
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unsigned int ov9640_regs_len, matrix_regs_len; |
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unsigned int i; |
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int ret; |
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u8 val; |
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/* select register configuration for given resolution */ |
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switch (width) { |
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case W_QQCIF: |
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ov9640_regs = ov9640_regs_qqcif; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif); |
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break; |
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case W_QQVGA: |
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ov9640_regs = ov9640_regs_qqvga; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga); |
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break; |
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case W_QCIF: |
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ov9640_regs = ov9640_regs_qcif; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif); |
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break; |
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case W_QVGA: |
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ov9640_regs = ov9640_regs_qvga; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga); |
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break; |
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case W_CIF: |
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ov9640_regs = ov9640_regs_cif; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif); |
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break; |
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case W_VGA: |
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ov9640_regs = ov9640_regs_vga; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga); |
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break; |
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case W_SXGA: |
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ov9640_regs = ov9640_regs_sxga; |
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ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga); |
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break; |
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default: |
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dev_err(&client->dev, "Failed to select resolution!\n"); |
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return -EINVAL; |
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} |
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/* select color matrix configuration for given color encoding */ |
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if (code == MEDIA_BUS_FMT_UYVY8_2X8) { |
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matrix_regs = ov9640_regs_yuv; |
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matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv); |
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} else { |
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matrix_regs = ov9640_regs_rgb; |
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matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb); |
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} |
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/* write register settings into the module */ |
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for (i = 0; i < ov9640_regs_len; i++) { |
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val = ov9640_regs[i].val; |
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switch (ov9640_regs[i].reg) { |
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case OV9640_COM7: |
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val |= alts->com7; |
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break; |
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case OV9640_COM12: |
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val |= alts->com12; |
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break; |
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case OV9640_COM13: |
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val |= alts->com13; |
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break; |
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case OV9640_COM15: |
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val |= alts->com15; |
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break; |
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} |
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ret = ov9640_reg_write(client, ov9640_regs[i].reg, val); |
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if (ret) |
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return ret; |
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} |
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/* write color matrix configuration into the module */ |
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for (i = 0; i < matrix_regs_len; i++) { |
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ret = ov9640_reg_write(client, matrix_regs[i].reg, |
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matrix_regs[i].val); |
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if (ret) |
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return ret; |
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} |
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return 0; |
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} |
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/* program default register values */ |
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static int ov9640_prog_dflt(struct i2c_client *client) |
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{ |
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unsigned int i; |
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int ret; |
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|
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for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) { |
|
ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg, |
|
ov9640_regs_dflt[i].val); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
/* wait for the changes to actually happen, 140ms are not enough yet */ |
|
msleep(150); |
|
|
|
return 0; |
|
} |
|
|
|
/* set the format we will capture in */ |
|
static int ov9640_s_fmt(struct v4l2_subdev *sd, |
|
struct v4l2_mbus_framefmt *mf) |
|
{ |
|
struct i2c_client *client = v4l2_get_subdevdata(sd); |
|
struct ov9640_reg_alt alts = {0}; |
|
int ret; |
|
|
|
ov9640_alter_regs(mf->code, &alts); |
|
|
|
ov9640_reset(client); |
|
|
|
ret = ov9640_prog_dflt(client); |
|
if (ret) |
|
return ret; |
|
|
|
return ov9640_write_regs(client, mf->width, mf->code, &alts); |
|
} |
|
|
|
static int ov9640_set_fmt(struct v4l2_subdev *sd, |
|
struct v4l2_subdev_state *sd_state, |
|
struct v4l2_subdev_format *format) |
|
{ |
|
struct v4l2_mbus_framefmt *mf = &format->format; |
|
|
|
if (format->pad) |
|
return -EINVAL; |
|
|
|
ov9640_res_roundup(&mf->width, &mf->height); |
|
|
|
mf->field = V4L2_FIELD_NONE; |
|
|
|
switch (mf->code) { |
|
case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE: |
|
case MEDIA_BUS_FMT_RGB565_2X8_LE: |
|
mf->colorspace = V4L2_COLORSPACE_SRGB; |
|
break; |
|
default: |
|
mf->code = MEDIA_BUS_FMT_UYVY8_2X8; |
|
fallthrough; |
|
case MEDIA_BUS_FMT_UYVY8_2X8: |
|
mf->colorspace = V4L2_COLORSPACE_JPEG; |
|
break; |
|
} |
|
|
|
if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
|
return ov9640_s_fmt(sd, mf); |
|
|
|
sd_state->pads->try_fmt = *mf; |
|
|
|
return 0; |
|
} |
|
|
|
static int ov9640_enum_mbus_code(struct v4l2_subdev *sd, |
|
struct v4l2_subdev_state *sd_state, |
|
struct v4l2_subdev_mbus_code_enum *code) |
|
{ |
|
if (code->pad || code->index >= ARRAY_SIZE(ov9640_codes)) |
|
return -EINVAL; |
|
|
|
code->code = ov9640_codes[code->index]; |
|
|
|
return 0; |
|
} |
|
|
|
static int ov9640_get_selection(struct v4l2_subdev *sd, |
|
struct v4l2_subdev_state *sd_state, |
|
struct v4l2_subdev_selection *sel) |
|
{ |
|
if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) |
|
return -EINVAL; |
|
|
|
sel->r.left = 0; |
|
sel->r.top = 0; |
|
switch (sel->target) { |
|
case V4L2_SEL_TGT_CROP_BOUNDS: |
|
case V4L2_SEL_TGT_CROP: |
|
sel->r.width = W_SXGA; |
|
sel->r.height = H_SXGA; |
|
return 0; |
|
default: |
|
return -EINVAL; |
|
} |
|
} |
|
|
|
static int ov9640_video_probe(struct i2c_client *client) |
|
{ |
|
struct v4l2_subdev *sd = i2c_get_clientdata(client); |
|
struct ov9640_priv *priv = to_ov9640_sensor(sd); |
|
u8 pid, ver, midh, midl; |
|
const char *devname; |
|
int ret; |
|
|
|
ret = ov9640_s_power(&priv->subdev, 1); |
|
if (ret < 0) |
|
return ret; |
|
|
|
/* |
|
* check and show product ID and manufacturer ID |
|
*/ |
|
|
|
ret = ov9640_reg_read(client, OV9640_PID, &pid); |
|
if (!ret) |
|
ret = ov9640_reg_read(client, OV9640_VER, &ver); |
|
if (!ret) |
|
ret = ov9640_reg_read(client, OV9640_MIDH, &midh); |
|
if (!ret) |
|
ret = ov9640_reg_read(client, OV9640_MIDL, &midl); |
|
if (ret) |
|
goto done; |
|
|
|
switch (VERSION(pid, ver)) { |
|
case OV9640_V2: |
|
devname = "ov9640"; |
|
priv->revision = 2; |
|
break; |
|
case OV9640_V3: |
|
devname = "ov9640"; |
|
priv->revision = 3; |
|
break; |
|
default: |
|
dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver); |
|
ret = -ENODEV; |
|
goto done; |
|
} |
|
|
|
dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n", |
|
devname, pid, ver, midh, midl); |
|
|
|
ret = v4l2_ctrl_handler_setup(&priv->hdl); |
|
|
|
done: |
|
ov9640_s_power(&priv->subdev, 0); |
|
return ret; |
|
} |
|
|
|
static const struct v4l2_ctrl_ops ov9640_ctrl_ops = { |
|
.s_ctrl = ov9640_s_ctrl, |
|
}; |
|
|
|
static const struct v4l2_subdev_core_ops ov9640_core_ops = { |
|
#ifdef CONFIG_VIDEO_ADV_DEBUG |
|
.g_register = ov9640_get_register, |
|
.s_register = ov9640_set_register, |
|
#endif |
|
.s_power = ov9640_s_power, |
|
}; |
|
|
|
/* Request bus settings on camera side */ |
|
static int ov9640_get_mbus_config(struct v4l2_subdev *sd, |
|
unsigned int pad, |
|
struct v4l2_mbus_config *cfg) |
|
{ |
|
cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER | |
|
V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH | |
|
V4L2_MBUS_DATA_ACTIVE_HIGH; |
|
cfg->type = V4L2_MBUS_PARALLEL; |
|
|
|
return 0; |
|
} |
|
|
|
static const struct v4l2_subdev_video_ops ov9640_video_ops = { |
|
.s_stream = ov9640_s_stream, |
|
}; |
|
|
|
static const struct v4l2_subdev_pad_ops ov9640_pad_ops = { |
|
.enum_mbus_code = ov9640_enum_mbus_code, |
|
.get_selection = ov9640_get_selection, |
|
.set_fmt = ov9640_set_fmt, |
|
.get_mbus_config = ov9640_get_mbus_config, |
|
}; |
|
|
|
static const struct v4l2_subdev_ops ov9640_subdev_ops = { |
|
.core = &ov9640_core_ops, |
|
.video = &ov9640_video_ops, |
|
.pad = &ov9640_pad_ops, |
|
}; |
|
|
|
/* |
|
* i2c_driver function |
|
*/ |
|
static int ov9640_probe(struct i2c_client *client, |
|
const struct i2c_device_id *did) |
|
{ |
|
struct ov9640_priv *priv; |
|
int ret; |
|
|
|
priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
|
if (!priv) |
|
return -ENOMEM; |
|
|
|
priv->gpio_power = devm_gpiod_get(&client->dev, "Camera power", |
|
GPIOD_OUT_LOW); |
|
if (IS_ERR(priv->gpio_power)) { |
|
ret = PTR_ERR(priv->gpio_power); |
|
return ret; |
|
} |
|
|
|
priv->gpio_reset = devm_gpiod_get(&client->dev, "Camera reset", |
|
GPIOD_OUT_HIGH); |
|
if (IS_ERR(priv->gpio_reset)) { |
|
ret = PTR_ERR(priv->gpio_reset); |
|
return ret; |
|
} |
|
|
|
v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops); |
|
|
|
v4l2_ctrl_handler_init(&priv->hdl, 2); |
|
v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops, |
|
V4L2_CID_VFLIP, 0, 1, 1, 0); |
|
v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops, |
|
V4L2_CID_HFLIP, 0, 1, 1, 0); |
|
|
|
if (priv->hdl.error) { |
|
ret = priv->hdl.error; |
|
goto ectrlinit; |
|
} |
|
|
|
priv->subdev.ctrl_handler = &priv->hdl; |
|
|
|
priv->clk = devm_clk_get(&client->dev, "mclk"); |
|
if (IS_ERR(priv->clk)) { |
|
ret = PTR_ERR(priv->clk); |
|
goto ectrlinit; |
|
} |
|
|
|
ret = ov9640_video_probe(client); |
|
if (ret) |
|
goto ectrlinit; |
|
|
|
priv->subdev.dev = &client->dev; |
|
ret = v4l2_async_register_subdev(&priv->subdev); |
|
if (ret) |
|
goto ectrlinit; |
|
|
|
return 0; |
|
|
|
ectrlinit: |
|
v4l2_ctrl_handler_free(&priv->hdl); |
|
|
|
return ret; |
|
} |
|
|
|
static int ov9640_remove(struct i2c_client *client) |
|
{ |
|
struct v4l2_subdev *sd = i2c_get_clientdata(client); |
|
struct ov9640_priv *priv = to_ov9640_sensor(sd); |
|
|
|
v4l2_async_unregister_subdev(&priv->subdev); |
|
v4l2_ctrl_handler_free(&priv->hdl); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct i2c_device_id ov9640_id[] = { |
|
{ "ov9640", 0 }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(i2c, ov9640_id); |
|
|
|
static struct i2c_driver ov9640_i2c_driver = { |
|
.driver = { |
|
.name = "ov9640", |
|
}, |
|
.probe = ov9640_probe, |
|
.remove = ov9640_remove, |
|
.id_table = ov9640_id, |
|
}; |
|
|
|
module_i2c_driver(ov9640_i2c_driver); |
|
|
|
MODULE_DESCRIPTION("OmniVision OV96xx CMOS Image Sensor driver"); |
|
MODULE_AUTHOR("Marek Vasut <[email protected]>"); |
|
MODULE_LICENSE("GPL v2");
|
|
|