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131 lines
3.3 KiB
131 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* drivers/irq/irq-nvic.c |
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* |
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* Copyright (C) 2008 ARM Limited, All Rights Reserved. |
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* Copyright (C) 2013 Pengutronix |
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* |
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* Support for the Nested Vectored Interrupt Controller found on the |
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* ARMv7-M CPUs (Cortex-M3/M4) |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqdomain.h> |
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#include <asm/v7m.h> |
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#include <asm/exception.h> |
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#define NVIC_ISER 0x000 |
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#define NVIC_ICER 0x080 |
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#define NVIC_IPR 0x300 |
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#define NVIC_MAX_BANKS 16 |
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/* |
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* Each bank handles 32 irqs. Only the 16th (= last) bank handles only |
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* 16 irqs. |
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*/ |
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#define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16) |
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static struct irq_domain *nvic_irq_domain; |
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asmlinkage void __exception_irq_entry |
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nvic_handle_irq(irq_hw_number_t hwirq, struct pt_regs *regs) |
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{ |
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handle_domain_irq(nvic_irq_domain, hwirq, regs); |
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} |
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static int nvic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *arg) |
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{ |
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int i, ret; |
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irq_hw_number_t hwirq; |
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unsigned int type = IRQ_TYPE_NONE; |
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struct irq_fwspec *fwspec = arg; |
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ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type); |
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if (ret) |
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return ret; |
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for (i = 0; i < nr_irqs; i++) |
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irq_map_generic_chip(domain, virq + i, hwirq + i); |
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return 0; |
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} |
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static const struct irq_domain_ops nvic_irq_domain_ops = { |
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.translate = irq_domain_translate_onecell, |
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.alloc = nvic_irq_domain_alloc, |
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.free = irq_domain_free_irqs_top, |
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}; |
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static int __init nvic_of_init(struct device_node *node, |
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struct device_node *parent) |
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{ |
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; |
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unsigned int irqs, i, ret, numbanks; |
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void __iomem *nvic_base; |
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numbanks = (readl_relaxed(V7M_SCS_ICTR) & |
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V7M_SCS_ICTR_INTLINESNUM_MASK) + 1; |
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nvic_base = of_iomap(node, 0); |
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if (!nvic_base) { |
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pr_warn("unable to map nvic registers\n"); |
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return -ENOMEM; |
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} |
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irqs = numbanks * 32; |
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if (irqs > NVIC_MAX_IRQ) |
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irqs = NVIC_MAX_IRQ; |
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nvic_irq_domain = |
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irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL); |
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if (!nvic_irq_domain) { |
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pr_warn("Failed to allocate irq domain\n"); |
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return -ENOMEM; |
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} |
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ret = irq_alloc_domain_generic_chips(nvic_irq_domain, 32, 1, |
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"nvic_irq", handle_fasteoi_irq, |
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clr, 0, IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_warn("Failed to allocate irq chips\n"); |
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irq_domain_remove(nvic_irq_domain); |
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return ret; |
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} |
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for (i = 0; i < numbanks; ++i) { |
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struct irq_chip_generic *gc; |
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gc = irq_get_domain_generic_chip(nvic_irq_domain, 32 * i); |
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gc->reg_base = nvic_base + 4 * i; |
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gc->chip_types[0].regs.enable = NVIC_ISER; |
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gc->chip_types[0].regs.disable = NVIC_ICER; |
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; |
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gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; |
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/* This is a no-op as end of interrupt is signaled by the |
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* exception return sequence. |
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*/ |
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gc->chip_types[0].chip.irq_eoi = irq_gc_noop; |
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/* disable interrupts */ |
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writel_relaxed(~0, gc->reg_base + NVIC_ICER); |
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} |
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/* Set priority on all interrupts */ |
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for (i = 0; i < irqs; i += 4) |
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writel_relaxed(0, nvic_base + NVIC_IPR + i); |
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return 0; |
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} |
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IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);
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