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578 lines
14 KiB
578 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* ARM GIC v2m MSI(-X) support |
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* Support for Message Signaled Interrupts for systems that |
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* implement ARM Generic Interrupt Controller: GICv2m. |
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* |
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* Copyright (C) 2014 Advanced Micro Devices, Inc. |
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* Authors: Suravee Suthikulpanit <[email protected]> |
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* Harish Kasiviswanathan <[email protected]> |
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* Brandon Anderson <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) "GICv2m: " fmt |
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|
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#include <linux/acpi.h> |
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#include <linux/dma-iommu.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/msi.h> |
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#include <linux/of_address.h> |
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#include <linux/of_pci.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/irqchip/arm-gic.h> |
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|
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/* |
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* MSI_TYPER: |
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* [31:26] Reserved |
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* [25:16] lowest SPI assigned to MSI |
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* [15:10] Reserved |
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* [9:0] Numer of SPIs assigned to MSI |
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*/ |
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#define V2M_MSI_TYPER 0x008 |
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#define V2M_MSI_TYPER_BASE_SHIFT 16 |
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#define V2M_MSI_TYPER_BASE_MASK 0x3FF |
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#define V2M_MSI_TYPER_NUM_MASK 0x3FF |
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#define V2M_MSI_SETSPI_NS 0x040 |
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#define V2M_MIN_SPI 32 |
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#define V2M_MAX_SPI 1019 |
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#define V2M_MSI_IIDR 0xFCC |
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|
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#define V2M_MSI_TYPER_BASE_SPI(x) \ |
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(((x) >> V2M_MSI_TYPER_BASE_SHIFT) & V2M_MSI_TYPER_BASE_MASK) |
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|
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#define V2M_MSI_TYPER_NUM_SPI(x) ((x) & V2M_MSI_TYPER_NUM_MASK) |
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|
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/* APM X-Gene with GICv2m MSI_IIDR register value */ |
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#define XGENE_GICV2M_MSI_IIDR 0x06000170 |
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|
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/* Broadcom NS2 GICv2m MSI_IIDR register value */ |
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#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f |
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|
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/* List of flags for specific v2m implementation */ |
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#define GICV2M_NEEDS_SPI_OFFSET 0x00000001 |
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#define GICV2M_GRAVITON_ADDRESS_ONLY 0x00000002 |
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|
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static LIST_HEAD(v2m_nodes); |
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static DEFINE_SPINLOCK(v2m_lock); |
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struct v2m_data { |
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struct list_head entry; |
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struct fwnode_handle *fwnode; |
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struct resource res; /* GICv2m resource */ |
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void __iomem *base; /* GICv2m virt address */ |
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u32 spi_start; /* The SPI number that MSIs start */ |
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u32 nr_spis; /* The number of SPIs for MSIs */ |
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u32 spi_offset; /* offset to be subtracted from SPI number */ |
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unsigned long *bm; /* MSI vector bitmap */ |
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u32 flags; /* v2m flags for specific implementation */ |
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}; |
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|
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static void gicv2m_mask_msi_irq(struct irq_data *d) |
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{ |
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pci_msi_mask_irq(d); |
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irq_chip_mask_parent(d); |
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} |
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|
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static void gicv2m_unmask_msi_irq(struct irq_data *d) |
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{ |
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pci_msi_unmask_irq(d); |
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irq_chip_unmask_parent(d); |
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} |
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static struct irq_chip gicv2m_msi_irq_chip = { |
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.name = "MSI", |
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.irq_mask = gicv2m_mask_msi_irq, |
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.irq_unmask = gicv2m_unmask_msi_irq, |
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.irq_eoi = irq_chip_eoi_parent, |
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.irq_write_msi_msg = pci_msi_domain_write_msg, |
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}; |
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static struct msi_domain_info gicv2m_msi_domain_info = { |
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
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MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), |
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.chip = &gicv2m_msi_irq_chip, |
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}; |
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static phys_addr_t gicv2m_get_msi_addr(struct v2m_data *v2m, int hwirq) |
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{ |
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if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) |
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return v2m->res.start | ((hwirq - 32) << 3); |
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else |
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return v2m->res.start + V2M_MSI_SETSPI_NS; |
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} |
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static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
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{ |
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struct v2m_data *v2m = irq_data_get_irq_chip_data(data); |
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phys_addr_t addr = gicv2m_get_msi_addr(v2m, data->hwirq); |
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msg->address_hi = upper_32_bits(addr); |
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msg->address_lo = lower_32_bits(addr); |
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if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) |
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msg->data = 0; |
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else |
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msg->data = data->hwirq; |
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if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) |
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msg->data -= v2m->spi_offset; |
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iommu_dma_compose_msi_msg(irq_data_get_msi_desc(data), msg); |
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} |
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static struct irq_chip gicv2m_irq_chip = { |
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.name = "GICv2m", |
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.irq_mask = irq_chip_mask_parent, |
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.irq_unmask = irq_chip_unmask_parent, |
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.irq_eoi = irq_chip_eoi_parent, |
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.irq_set_affinity = irq_chip_set_affinity_parent, |
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.irq_compose_msi_msg = gicv2m_compose_msi_msg, |
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}; |
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static int gicv2m_irq_gic_domain_alloc(struct irq_domain *domain, |
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unsigned int virq, |
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irq_hw_number_t hwirq) |
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{ |
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struct irq_fwspec fwspec; |
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struct irq_data *d; |
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int err; |
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if (is_of_node(domain->parent->fwnode)) { |
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fwspec.fwnode = domain->parent->fwnode; |
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fwspec.param_count = 3; |
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fwspec.param[0] = 0; |
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fwspec.param[1] = hwirq - 32; |
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fwspec.param[2] = IRQ_TYPE_EDGE_RISING; |
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} else if (is_fwnode_irqchip(domain->parent->fwnode)) { |
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fwspec.fwnode = domain->parent->fwnode; |
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fwspec.param_count = 2; |
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fwspec.param[0] = hwirq; |
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fwspec.param[1] = IRQ_TYPE_EDGE_RISING; |
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} else { |
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return -EINVAL; |
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} |
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec); |
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if (err) |
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return err; |
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/* Configure the interrupt line to be edge */ |
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d = irq_domain_get_irq_data(domain->parent, virq); |
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d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING); |
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return 0; |
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} |
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static void gicv2m_unalloc_msi(struct v2m_data *v2m, unsigned int hwirq, |
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int nr_irqs) |
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{ |
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spin_lock(&v2m_lock); |
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bitmap_release_region(v2m->bm, hwirq - v2m->spi_start, |
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get_count_order(nr_irqs)); |
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spin_unlock(&v2m_lock); |
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} |
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static int gicv2m_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *args) |
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{ |
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msi_alloc_info_t *info = args; |
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struct v2m_data *v2m = NULL, *tmp; |
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int hwirq, offset, i, err = 0; |
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spin_lock(&v2m_lock); |
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list_for_each_entry(tmp, &v2m_nodes, entry) { |
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offset = bitmap_find_free_region(tmp->bm, tmp->nr_spis, |
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get_count_order(nr_irqs)); |
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if (offset >= 0) { |
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v2m = tmp; |
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break; |
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} |
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} |
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spin_unlock(&v2m_lock); |
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if (!v2m) |
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return -ENOSPC; |
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hwirq = v2m->spi_start + offset; |
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err = iommu_dma_prepare_msi(info->desc, |
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gicv2m_get_msi_addr(v2m, hwirq)); |
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if (err) |
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return err; |
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for (i = 0; i < nr_irqs; i++) { |
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err = gicv2m_irq_gic_domain_alloc(domain, virq + i, hwirq + i); |
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if (err) |
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goto fail; |
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irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, |
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&gicv2m_irq_chip, v2m); |
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} |
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return 0; |
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fail: |
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irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
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gicv2m_unalloc_msi(v2m, hwirq, nr_irqs); |
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return err; |
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} |
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static void gicv2m_irq_domain_free(struct irq_domain *domain, |
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unsigned int virq, unsigned int nr_irqs) |
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{ |
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struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
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struct v2m_data *v2m = irq_data_get_irq_chip_data(d); |
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gicv2m_unalloc_msi(v2m, d->hwirq, nr_irqs); |
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irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
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} |
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static const struct irq_domain_ops gicv2m_domain_ops = { |
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.alloc = gicv2m_irq_domain_alloc, |
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.free = gicv2m_irq_domain_free, |
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}; |
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static bool is_msi_spi_valid(u32 base, u32 num) |
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{ |
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if (base < V2M_MIN_SPI) { |
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pr_err("Invalid MSI base SPI (base:%u)\n", base); |
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return false; |
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} |
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if ((num == 0) || (base + num > V2M_MAX_SPI)) { |
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pr_err("Number of SPIs (%u) exceed maximum (%u)\n", |
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num, V2M_MAX_SPI - V2M_MIN_SPI + 1); |
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return false; |
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} |
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return true; |
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} |
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static struct irq_chip gicv2m_pmsi_irq_chip = { |
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.name = "pMSI", |
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}; |
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static struct msi_domain_ops gicv2m_pmsi_ops = { |
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}; |
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static struct msi_domain_info gicv2m_pmsi_domain_info = { |
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), |
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.ops = &gicv2m_pmsi_ops, |
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.chip = &gicv2m_pmsi_irq_chip, |
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}; |
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static void gicv2m_teardown(void) |
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{ |
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struct v2m_data *v2m, *tmp; |
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list_for_each_entry_safe(v2m, tmp, &v2m_nodes, entry) { |
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list_del(&v2m->entry); |
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bitmap_free(v2m->bm); |
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iounmap(v2m->base); |
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of_node_put(to_of_node(v2m->fwnode)); |
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if (is_fwnode_irqchip(v2m->fwnode)) |
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irq_domain_free_fwnode(v2m->fwnode); |
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kfree(v2m); |
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} |
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} |
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static int gicv2m_allocate_domains(struct irq_domain *parent) |
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{ |
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struct irq_domain *inner_domain, *pci_domain, *plat_domain; |
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struct v2m_data *v2m; |
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v2m = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry); |
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if (!v2m) |
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return 0; |
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inner_domain = irq_domain_create_tree(v2m->fwnode, |
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&gicv2m_domain_ops, v2m); |
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if (!inner_domain) { |
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pr_err("Failed to create GICv2m domain\n"); |
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return -ENOMEM; |
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} |
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irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); |
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inner_domain->parent = parent; |
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pci_domain = pci_msi_create_irq_domain(v2m->fwnode, |
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&gicv2m_msi_domain_info, |
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inner_domain); |
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plat_domain = platform_msi_create_irq_domain(v2m->fwnode, |
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&gicv2m_pmsi_domain_info, |
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inner_domain); |
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if (!pci_domain || !plat_domain) { |
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pr_err("Failed to create MSI domains\n"); |
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if (plat_domain) |
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irq_domain_remove(plat_domain); |
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if (pci_domain) |
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irq_domain_remove(pci_domain); |
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irq_domain_remove(inner_domain); |
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return -ENOMEM; |
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} |
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return 0; |
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} |
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static int __init gicv2m_init_one(struct fwnode_handle *fwnode, |
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u32 spi_start, u32 nr_spis, |
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struct resource *res, u32 flags) |
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{ |
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int ret; |
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struct v2m_data *v2m; |
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v2m = kzalloc(sizeof(struct v2m_data), GFP_KERNEL); |
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if (!v2m) |
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return -ENOMEM; |
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INIT_LIST_HEAD(&v2m->entry); |
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v2m->fwnode = fwnode; |
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v2m->flags = flags; |
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memcpy(&v2m->res, res, sizeof(struct resource)); |
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v2m->base = ioremap(v2m->res.start, resource_size(&v2m->res)); |
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if (!v2m->base) { |
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pr_err("Failed to map GICv2m resource\n"); |
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ret = -ENOMEM; |
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goto err_free_v2m; |
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} |
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if (spi_start && nr_spis) { |
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v2m->spi_start = spi_start; |
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v2m->nr_spis = nr_spis; |
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} else { |
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u32 typer; |
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/* Graviton should always have explicit spi_start/nr_spis */ |
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if (v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY) { |
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ret = -EINVAL; |
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goto err_iounmap; |
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} |
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typer = readl_relaxed(v2m->base + V2M_MSI_TYPER); |
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v2m->spi_start = V2M_MSI_TYPER_BASE_SPI(typer); |
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v2m->nr_spis = V2M_MSI_TYPER_NUM_SPI(typer); |
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} |
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if (!is_msi_spi_valid(v2m->spi_start, v2m->nr_spis)) { |
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ret = -EINVAL; |
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goto err_iounmap; |
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} |
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|
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/* |
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* APM X-Gene GICv2m implementation has an erratum where |
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* the MSI data needs to be the offset from the spi_start |
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* in order to trigger the correct MSI interrupt. This is |
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* different from the standard GICv2m implementation where |
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* the MSI data is the absolute value within the range from |
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* spi_start to (spi_start + num_spis). |
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* |
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* Broadcom NS2 GICv2m implementation has an erratum where the MSI data |
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* is 'spi_number - 32' |
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* |
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* Reading that register fails on the Graviton implementation |
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*/ |
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if (!(v2m->flags & GICV2M_GRAVITON_ADDRESS_ONLY)) { |
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switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) { |
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case XGENE_GICV2M_MSI_IIDR: |
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v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; |
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v2m->spi_offset = v2m->spi_start; |
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break; |
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case BCM_NS2_GICV2M_MSI_IIDR: |
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v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; |
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v2m->spi_offset = 32; |
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break; |
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} |
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} |
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v2m->bm = bitmap_zalloc(v2m->nr_spis, GFP_KERNEL); |
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if (!v2m->bm) { |
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ret = -ENOMEM; |
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goto err_iounmap; |
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} |
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list_add_tail(&v2m->entry, &v2m_nodes); |
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pr_info("range%pR, SPI[%d:%d]\n", res, |
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v2m->spi_start, (v2m->spi_start + v2m->nr_spis - 1)); |
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return 0; |
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err_iounmap: |
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iounmap(v2m->base); |
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err_free_v2m: |
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kfree(v2m); |
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return ret; |
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} |
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static struct of_device_id gicv2m_device_id[] = { |
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{ .compatible = "arm,gic-v2m-frame", }, |
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{}, |
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}; |
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static int __init gicv2m_of_init(struct fwnode_handle *parent_handle, |
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struct irq_domain *parent) |
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{ |
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int ret = 0; |
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struct device_node *node = to_of_node(parent_handle); |
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struct device_node *child; |
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for (child = of_find_matching_node(node, gicv2m_device_id); child; |
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child = of_find_matching_node(child, gicv2m_device_id)) { |
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u32 spi_start = 0, nr_spis = 0; |
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struct resource res; |
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|
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if (!of_find_property(child, "msi-controller", NULL)) |
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continue; |
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ret = of_address_to_resource(child, 0, &res); |
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if (ret) { |
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pr_err("Failed to allocate v2m resource.\n"); |
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break; |
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} |
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if (!of_property_read_u32(child, "arm,msi-base-spi", |
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&spi_start) && |
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!of_property_read_u32(child, "arm,msi-num-spis", &nr_spis)) |
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pr_info("DT overriding V2M MSI_TYPER (base:%u, num:%u)\n", |
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spi_start, nr_spis); |
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ret = gicv2m_init_one(&child->fwnode, spi_start, nr_spis, |
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&res, 0); |
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if (ret) { |
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of_node_put(child); |
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break; |
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} |
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} |
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|
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if (!ret) |
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ret = gicv2m_allocate_domains(parent); |
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if (ret) |
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gicv2m_teardown(); |
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return ret; |
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} |
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|
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#ifdef CONFIG_ACPI |
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static int acpi_num_msi; |
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|
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static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev) |
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{ |
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struct v2m_data *data; |
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|
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if (WARN_ON(acpi_num_msi <= 0)) |
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return NULL; |
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|
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/* We only return the fwnode of the first MSI frame. */ |
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data = list_first_entry_or_null(&v2m_nodes, struct v2m_data, entry); |
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if (!data) |
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return NULL; |
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|
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return data->fwnode; |
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} |
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static bool acpi_check_amazon_graviton_quirks(void) |
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{ |
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static struct acpi_table_madt *madt; |
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acpi_status status; |
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bool rc = false; |
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|
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#define ACPI_AMZN_OEM_ID "AMAZON" |
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status = acpi_get_table(ACPI_SIG_MADT, 0, |
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(struct acpi_table_header **)&madt); |
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|
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if (ACPI_FAILURE(status) || !madt) |
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return rc; |
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rc = !memcmp(madt->header.oem_id, ACPI_AMZN_OEM_ID, ACPI_OEM_ID_SIZE); |
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acpi_put_table((struct acpi_table_header *)madt); |
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|
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return rc; |
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} |
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|
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static int __init |
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acpi_parse_madt_msi(union acpi_subtable_headers *header, |
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const unsigned long end) |
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{ |
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int ret; |
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struct resource res; |
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u32 spi_start = 0, nr_spis = 0; |
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struct acpi_madt_generic_msi_frame *m; |
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struct fwnode_handle *fwnode; |
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u32 flags = 0; |
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|
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m = (struct acpi_madt_generic_msi_frame *)header; |
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if (BAD_MADT_ENTRY(m, end)) |
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return -EINVAL; |
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|
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res.start = m->base_address; |
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res.end = m->base_address + SZ_4K - 1; |
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res.flags = IORESOURCE_MEM; |
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|
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if (acpi_check_amazon_graviton_quirks()) { |
|
pr_info("applying Amazon Graviton quirk\n"); |
|
res.end = res.start + SZ_8K - 1; |
|
flags |= GICV2M_GRAVITON_ADDRESS_ONLY; |
|
gicv2m_msi_domain_info.flags &= ~MSI_FLAG_MULTI_PCI_MSI; |
|
} |
|
|
|
if (m->flags & ACPI_MADT_OVERRIDE_SPI_VALUES) { |
|
spi_start = m->spi_base; |
|
nr_spis = m->spi_count; |
|
|
|
pr_info("ACPI overriding V2M MSI_TYPER (base:%u, num:%u)\n", |
|
spi_start, nr_spis); |
|
} |
|
|
|
fwnode = irq_domain_alloc_fwnode(&res.start); |
|
if (!fwnode) { |
|
pr_err("Unable to allocate GICv2m domain token\n"); |
|
return -EINVAL; |
|
} |
|
|
|
ret = gicv2m_init_one(fwnode, spi_start, nr_spis, &res, flags); |
|
if (ret) |
|
irq_domain_free_fwnode(fwnode); |
|
|
|
return ret; |
|
} |
|
|
|
static int __init gicv2m_acpi_init(struct irq_domain *parent) |
|
{ |
|
int ret; |
|
|
|
if (acpi_num_msi > 0) |
|
return 0; |
|
|
|
acpi_num_msi = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_MSI_FRAME, |
|
acpi_parse_madt_msi, 0); |
|
|
|
if (acpi_num_msi <= 0) |
|
goto err_out; |
|
|
|
ret = gicv2m_allocate_domains(parent); |
|
if (ret) |
|
goto err_out; |
|
|
|
pci_msi_register_fwnode_provider(&gicv2m_get_fwnode); |
|
|
|
return 0; |
|
|
|
err_out: |
|
gicv2m_teardown(); |
|
return -EINVAL; |
|
} |
|
#else /* CONFIG_ACPI */ |
|
static int __init gicv2m_acpi_init(struct irq_domain *parent) |
|
{ |
|
return -EINVAL; |
|
} |
|
#endif /* CONFIG_ACPI */ |
|
|
|
int __init gicv2m_init(struct fwnode_handle *parent_handle, |
|
struct irq_domain *parent) |
|
{ |
|
if (is_of_node(parent_handle)) |
|
return gicv2m_of_init(parent_handle, parent); |
|
|
|
return gicv2m_acpi_init(parent); |
|
}
|
|
|