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287 lines
7.0 KiB
287 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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/* FIC Registers */ |
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#define AL_FIC_CAUSE 0x00 |
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#define AL_FIC_SET_CAUSE 0x08 |
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#define AL_FIC_MASK 0x10 |
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#define AL_FIC_CONTROL 0x28 |
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#define CONTROL_TRIGGER_RISING BIT(3) |
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#define CONTROL_MASK_MSI_X BIT(5) |
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#define NR_FIC_IRQS 32 |
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MODULE_AUTHOR("Talel Shenhar"); |
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MODULE_DESCRIPTION("Amazon's Annapurna Labs Interrupt Controller Driver"); |
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MODULE_LICENSE("GPL v2"); |
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enum al_fic_state { |
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AL_FIC_UNCONFIGURED = 0, |
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AL_FIC_CONFIGURED_LEVEL, |
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AL_FIC_CONFIGURED_RISING_EDGE, |
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}; |
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struct al_fic { |
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void __iomem *base; |
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struct irq_domain *domain; |
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const char *name; |
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unsigned int parent_irq; |
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enum al_fic_state state; |
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}; |
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static void al_fic_set_trigger(struct al_fic *fic, |
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struct irq_chip_generic *gc, |
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enum al_fic_state new_state) |
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{ |
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irq_flow_handler_t handler; |
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u32 control = readl_relaxed(fic->base + AL_FIC_CONTROL); |
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if (new_state == AL_FIC_CONFIGURED_LEVEL) { |
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handler = handle_level_irq; |
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control &= ~CONTROL_TRIGGER_RISING; |
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} else { |
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handler = handle_edge_irq; |
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control |= CONTROL_TRIGGER_RISING; |
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} |
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gc->chip_types->handler = handler; |
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fic->state = new_state; |
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writel_relaxed(control, fic->base + AL_FIC_CONTROL); |
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} |
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static int al_fic_irq_set_type(struct irq_data *data, unsigned int flow_type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
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struct al_fic *fic = gc->private; |
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enum al_fic_state new_state; |
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int ret = 0; |
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irq_gc_lock(gc); |
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if (((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH) && |
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((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_EDGE_RISING)) { |
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pr_debug("fic doesn't support flow type %d\n", flow_type); |
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ret = -EINVAL; |
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goto err; |
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} |
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new_state = (flow_type & IRQ_TYPE_LEVEL_HIGH) ? |
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AL_FIC_CONFIGURED_LEVEL : AL_FIC_CONFIGURED_RISING_EDGE; |
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/* |
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* A given FIC instance can be either all level or all edge triggered. |
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* This is generally fixed depending on what pieces of HW it's wired up |
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* to. |
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* |
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* We configure it based on the sensitivity of the first source |
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* being setup, and reject any subsequent attempt at configuring it in a |
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* different way. |
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*/ |
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if (fic->state == AL_FIC_UNCONFIGURED) { |
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al_fic_set_trigger(fic, gc, new_state); |
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} else if (fic->state != new_state) { |
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pr_debug("fic %s state already configured to %d\n", |
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fic->name, fic->state); |
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ret = -EINVAL; |
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goto err; |
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} |
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err: |
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irq_gc_unlock(gc); |
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return ret; |
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} |
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static void al_fic_irq_handler(struct irq_desc *desc) |
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{ |
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struct al_fic *fic = irq_desc_get_handler_data(desc); |
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struct irq_domain *domain = fic->domain; |
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struct irq_chip *irqchip = irq_desc_get_chip(desc); |
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0); |
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unsigned long pending; |
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u32 hwirq; |
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chained_irq_enter(irqchip, desc); |
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pending = readl_relaxed(fic->base + AL_FIC_CAUSE); |
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pending &= ~gc->mask_cache; |
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for_each_set_bit(hwirq, &pending, NR_FIC_IRQS) |
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generic_handle_domain_irq(domain, hwirq); |
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chained_irq_exit(irqchip, desc); |
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} |
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static int al_fic_irq_retrigger(struct irq_data *data) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); |
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struct al_fic *fic = gc->private; |
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writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE); |
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return 1; |
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} |
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static int al_fic_register(struct device_node *node, |
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struct al_fic *fic) |
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{ |
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struct irq_chip_generic *gc; |
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int ret; |
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fic->domain = irq_domain_add_linear(node, |
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NR_FIC_IRQS, |
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&irq_generic_chip_ops, |
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fic); |
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if (!fic->domain) { |
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pr_err("fail to add irq domain\n"); |
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return -ENOMEM; |
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} |
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ret = irq_alloc_domain_generic_chips(fic->domain, |
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NR_FIC_IRQS, |
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1, fic->name, |
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handle_level_irq, |
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0, 0, IRQ_GC_INIT_MASK_CACHE); |
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if (ret) { |
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pr_err("fail to allocate generic chip (%d)\n", ret); |
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goto err_domain_remove; |
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} |
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gc = irq_get_domain_generic_chip(fic->domain, 0); |
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gc->reg_base = fic->base; |
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gc->chip_types->regs.mask = AL_FIC_MASK; |
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gc->chip_types->regs.ack = AL_FIC_CAUSE; |
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gc->chip_types->chip.irq_mask = irq_gc_mask_set_bit; |
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gc->chip_types->chip.irq_unmask = irq_gc_mask_clr_bit; |
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gc->chip_types->chip.irq_ack = irq_gc_ack_clr_bit; |
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gc->chip_types->chip.irq_set_type = al_fic_irq_set_type; |
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gc->chip_types->chip.irq_retrigger = al_fic_irq_retrigger; |
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gc->chip_types->chip.flags = IRQCHIP_SKIP_SET_WAKE; |
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gc->private = fic; |
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irq_set_chained_handler_and_data(fic->parent_irq, |
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al_fic_irq_handler, |
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fic); |
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return 0; |
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err_domain_remove: |
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irq_domain_remove(fic->domain); |
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return ret; |
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} |
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/* |
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* al_fic_wire_init() - initialize and configure fic in wire mode |
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* @of_node: optional pointer to interrupt controller's device tree node. |
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* @base: mmio to fic register |
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* @name: name of the fic |
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* @parent_irq: interrupt of parent |
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* |
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* This API will configure the fic hardware to to work in wire mode. |
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* In wire mode, fic hardware is generating a wire ("wired") interrupt. |
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* Interrupt can be generated based on positive edge or level - configuration is |
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* to be determined based on connected hardware to this fic. |
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*/ |
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static struct al_fic *al_fic_wire_init(struct device_node *node, |
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void __iomem *base, |
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const char *name, |
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unsigned int parent_irq) |
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{ |
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struct al_fic *fic; |
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int ret; |
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u32 control = CONTROL_MASK_MSI_X; |
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fic = kzalloc(sizeof(*fic), GFP_KERNEL); |
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if (!fic) |
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return ERR_PTR(-ENOMEM); |
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fic->base = base; |
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fic->parent_irq = parent_irq; |
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fic->name = name; |
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/* mask out all interrupts */ |
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writel_relaxed(0xFFFFFFFF, fic->base + AL_FIC_MASK); |
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/* clear any pending interrupt */ |
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writel_relaxed(0, fic->base + AL_FIC_CAUSE); |
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writel_relaxed(control, fic->base + AL_FIC_CONTROL); |
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ret = al_fic_register(node, fic); |
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if (ret) { |
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pr_err("fail to register irqchip\n"); |
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goto err_free; |
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} |
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pr_debug("%s initialized successfully in Legacy mode (parent-irq=%u)\n", |
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fic->name, parent_irq); |
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return fic; |
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err_free: |
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kfree(fic); |
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return ERR_PTR(ret); |
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} |
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static int __init al_fic_init_dt(struct device_node *node, |
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struct device_node *parent) |
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{ |
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int ret; |
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void __iomem *base; |
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unsigned int parent_irq; |
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struct al_fic *fic; |
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if (!parent) { |
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pr_err("%s: unsupported - device require a parent\n", |
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node->name); |
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return -EINVAL; |
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} |
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base = of_iomap(node, 0); |
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if (!base) { |
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pr_err("%s: fail to map memory\n", node->name); |
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return -ENOMEM; |
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} |
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parent_irq = irq_of_parse_and_map(node, 0); |
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if (!parent_irq) { |
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pr_err("%s: fail to map irq\n", node->name); |
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ret = -EINVAL; |
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goto err_unmap; |
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} |
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fic = al_fic_wire_init(node, |
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base, |
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node->name, |
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parent_irq); |
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if (IS_ERR(fic)) { |
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pr_err("%s: fail to initialize irqchip (%lu)\n", |
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node->name, |
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PTR_ERR(fic)); |
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ret = PTR_ERR(fic); |
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goto err_irq_dispose; |
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} |
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return 0; |
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err_irq_dispose: |
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irq_dispose_mapping(parent_irq); |
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err_unmap: |
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iounmap(base); |
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return ret; |
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} |
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IRQCHIP_DECLARE(al_fic, "amazon,al-fic", al_fic_init_dt);
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