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692 lines
17 KiB
692 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Analog Devices AD7768-1 SPI ADC driver |
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* |
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* Copyright 2017 Analog Devices Inc. |
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*/ |
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#include <linux/bitfield.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/err.h> |
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#include <linux/gpio/consumer.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/sysfs.h> |
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#include <linux/spi/spi.h> |
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|
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#include <linux/iio/buffer.h> |
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#include <linux/iio/iio.h> |
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#include <linux/iio/sysfs.h> |
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#include <linux/iio/trigger.h> |
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#include <linux/iio/triggered_buffer.h> |
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#include <linux/iio/trigger_consumer.h> |
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|
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/* AD7768 registers definition */ |
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#define AD7768_REG_CHIP_TYPE 0x3 |
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#define AD7768_REG_PROD_ID_L 0x4 |
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#define AD7768_REG_PROD_ID_H 0x5 |
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#define AD7768_REG_CHIP_GRADE 0x6 |
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#define AD7768_REG_SCRATCH_PAD 0x0A |
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#define AD7768_REG_VENDOR_L 0x0C |
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#define AD7768_REG_VENDOR_H 0x0D |
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#define AD7768_REG_INTERFACE_FORMAT 0x14 |
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#define AD7768_REG_POWER_CLOCK 0x15 |
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#define AD7768_REG_ANALOG 0x16 |
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#define AD7768_REG_ANALOG2 0x17 |
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#define AD7768_REG_CONVERSION 0x18 |
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#define AD7768_REG_DIGITAL_FILTER 0x19 |
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#define AD7768_REG_SINC3_DEC_RATE_MSB 0x1A |
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#define AD7768_REG_SINC3_DEC_RATE_LSB 0x1B |
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#define AD7768_REG_DUTY_CYCLE_RATIO 0x1C |
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#define AD7768_REG_SYNC_RESET 0x1D |
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#define AD7768_REG_GPIO_CONTROL 0x1E |
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#define AD7768_REG_GPIO_WRITE 0x1F |
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#define AD7768_REG_GPIO_READ 0x20 |
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#define AD7768_REG_OFFSET_HI 0x21 |
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#define AD7768_REG_OFFSET_MID 0x22 |
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#define AD7768_REG_OFFSET_LO 0x23 |
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#define AD7768_REG_GAIN_HI 0x24 |
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#define AD7768_REG_GAIN_MID 0x25 |
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#define AD7768_REG_GAIN_LO 0x26 |
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#define AD7768_REG_SPI_DIAG_ENABLE 0x28 |
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#define AD7768_REG_ADC_DIAG_ENABLE 0x29 |
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#define AD7768_REG_DIG_DIAG_ENABLE 0x2A |
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#define AD7768_REG_ADC_DATA 0x2C |
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#define AD7768_REG_MASTER_STATUS 0x2D |
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#define AD7768_REG_SPI_DIAG_STATUS 0x2E |
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#define AD7768_REG_ADC_DIAG_STATUS 0x2F |
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#define AD7768_REG_DIG_DIAG_STATUS 0x30 |
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#define AD7768_REG_MCLK_COUNTER 0x31 |
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/* AD7768_REG_POWER_CLOCK */ |
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#define AD7768_PWR_MCLK_DIV_MSK GENMASK(5, 4) |
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#define AD7768_PWR_MCLK_DIV(x) FIELD_PREP(AD7768_PWR_MCLK_DIV_MSK, x) |
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#define AD7768_PWR_PWRMODE_MSK GENMASK(1, 0) |
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#define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) |
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|
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/* AD7768_REG_DIGITAL_FILTER */ |
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#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) |
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#define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) |
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#define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) |
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#define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) |
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|
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/* AD7768_REG_CONVERSION */ |
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#define AD7768_CONV_MODE_MSK GENMASK(2, 0) |
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#define AD7768_CONV_MODE(x) FIELD_PREP(AD7768_CONV_MODE_MSK, x) |
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#define AD7768_RD_FLAG_MSK(x) (BIT(6) | ((x) & 0x3F)) |
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#define AD7768_WR_FLAG_MSK(x) ((x) & 0x3F) |
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enum ad7768_conv_mode { |
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AD7768_CONTINUOUS, |
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AD7768_ONE_SHOT, |
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AD7768_SINGLE, |
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AD7768_PERIODIC, |
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AD7768_STANDBY |
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}; |
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enum ad7768_pwrmode { |
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AD7768_ECO_MODE = 0, |
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AD7768_MED_MODE = 2, |
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AD7768_FAST_MODE = 3 |
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}; |
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enum ad7768_mclk_div { |
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AD7768_MCLK_DIV_16, |
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AD7768_MCLK_DIV_8, |
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AD7768_MCLK_DIV_4, |
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AD7768_MCLK_DIV_2 |
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}; |
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enum ad7768_dec_rate { |
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AD7768_DEC_RATE_32 = 0, |
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AD7768_DEC_RATE_64 = 1, |
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AD7768_DEC_RATE_128 = 2, |
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AD7768_DEC_RATE_256 = 3, |
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AD7768_DEC_RATE_512 = 4, |
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AD7768_DEC_RATE_1024 = 5, |
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AD7768_DEC_RATE_8 = 9, |
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AD7768_DEC_RATE_16 = 10 |
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}; |
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struct ad7768_clk_configuration { |
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enum ad7768_mclk_div mclk_div; |
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enum ad7768_dec_rate dec_rate; |
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unsigned int clk_div; |
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enum ad7768_pwrmode pwrmode; |
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}; |
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static const struct ad7768_clk_configuration ad7768_clk_config[] = { |
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, |
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, |
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, |
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, |
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{ AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, |
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, |
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, |
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, |
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{ AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, |
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{ AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, |
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{ AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, |
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}; |
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static const struct iio_chan_spec ad7768_channels[] = { |
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{ |
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.type = IIO_VOLTAGE, |
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), |
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), |
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), |
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.indexed = 1, |
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.channel = 0, |
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.scan_index = 0, |
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.scan_type = { |
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.sign = 'u', |
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.realbits = 24, |
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.storagebits = 32, |
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.shift = 8, |
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.endianness = IIO_BE, |
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}, |
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}, |
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}; |
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struct ad7768_state { |
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struct spi_device *spi; |
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struct regulator *vref; |
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struct mutex lock; |
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struct clk *mclk; |
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unsigned int mclk_freq; |
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unsigned int samp_freq; |
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struct completion completion; |
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struct iio_trigger *trig; |
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struct gpio_desc *gpio_sync_in; |
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const char *labels[ARRAY_SIZE(ad7768_channels)]; |
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/* |
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* DMA (thus cache coherency maintenance) requires the |
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* transfer buffers to live in their own cache lines. |
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*/ |
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union { |
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struct { |
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__be32 chan; |
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s64 timestamp; |
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} scan; |
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__be32 d32; |
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u8 d8[2]; |
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} data ____cacheline_aligned; |
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}; |
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static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr, |
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unsigned int len) |
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{ |
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unsigned int shift; |
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int ret; |
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shift = 32 - (8 * len); |
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st->data.d8[0] = AD7768_RD_FLAG_MSK(addr); |
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ret = spi_write_then_read(st->spi, st->data.d8, 1, |
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&st->data.d32, len); |
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if (ret < 0) |
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return ret; |
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return (be32_to_cpu(st->data.d32) >> shift); |
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} |
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static int ad7768_spi_reg_write(struct ad7768_state *st, |
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unsigned int addr, |
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unsigned int val) |
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{ |
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st->data.d8[0] = AD7768_WR_FLAG_MSK(addr); |
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st->data.d8[1] = val & 0xFF; |
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return spi_write(st->spi, st->data.d8, 2); |
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} |
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static int ad7768_set_mode(struct ad7768_state *st, |
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enum ad7768_conv_mode mode) |
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{ |
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int regval; |
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regval = ad7768_spi_reg_read(st, AD7768_REG_CONVERSION, 1); |
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if (regval < 0) |
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return regval; |
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regval &= ~AD7768_CONV_MODE_MSK; |
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regval |= AD7768_CONV_MODE(mode); |
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return ad7768_spi_reg_write(st, AD7768_REG_CONVERSION, regval); |
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} |
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static int ad7768_scan_direct(struct iio_dev *indio_dev) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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int readval, ret; |
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reinit_completion(&st->completion); |
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ret = ad7768_set_mode(st, AD7768_ONE_SHOT); |
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if (ret < 0) |
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return ret; |
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ret = wait_for_completion_timeout(&st->completion, |
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msecs_to_jiffies(1000)); |
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if (!ret) |
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return -ETIMEDOUT; |
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readval = ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); |
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if (readval < 0) |
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return readval; |
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/* |
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* Any SPI configuration of the AD7768-1 can only be |
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* performed in continuous conversion mode. |
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*/ |
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ret = ad7768_set_mode(st, AD7768_CONTINUOUS); |
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if (ret < 0) |
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return ret; |
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return readval; |
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} |
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static int ad7768_reg_access(struct iio_dev *indio_dev, |
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unsigned int reg, |
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unsigned int writeval, |
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unsigned int *readval) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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int ret; |
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mutex_lock(&st->lock); |
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if (readval) { |
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ret = ad7768_spi_reg_read(st, reg, 1); |
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if (ret < 0) |
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goto err_unlock; |
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*readval = ret; |
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ret = 0; |
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} else { |
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ret = ad7768_spi_reg_write(st, reg, writeval); |
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} |
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err_unlock: |
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mutex_unlock(&st->lock); |
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return ret; |
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} |
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static int ad7768_set_dig_fil(struct ad7768_state *st, |
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enum ad7768_dec_rate dec_rate) |
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{ |
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unsigned int mode; |
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int ret; |
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if (dec_rate == AD7768_DEC_RATE_8 || dec_rate == AD7768_DEC_RATE_16) |
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mode = AD7768_DIG_FIL_FIL(dec_rate); |
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else |
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mode = AD7768_DIG_FIL_DEC_RATE(dec_rate); |
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ret = ad7768_spi_reg_write(st, AD7768_REG_DIGITAL_FILTER, mode); |
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if (ret < 0) |
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return ret; |
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/* A sync-in pulse is required every time the filter dec rate changes */ |
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gpiod_set_value(st->gpio_sync_in, 1); |
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gpiod_set_value(st->gpio_sync_in, 0); |
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return 0; |
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} |
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static int ad7768_set_freq(struct ad7768_state *st, |
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unsigned int freq) |
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{ |
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unsigned int diff_new, diff_old, pwr_mode, i, idx; |
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int res, ret; |
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diff_old = U32_MAX; |
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idx = 0; |
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res = DIV_ROUND_CLOSEST(st->mclk_freq, freq); |
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|
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/* Find the closest match for the desired sampling frequency */ |
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for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { |
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diff_new = abs(res - ad7768_clk_config[i].clk_div); |
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if (diff_new < diff_old) { |
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diff_old = diff_new; |
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idx = i; |
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} |
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} |
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/* |
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* Set both the mclk_div and pwrmode with a single write to the |
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* POWER_CLOCK register |
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*/ |
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pwr_mode = AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | |
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AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); |
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ret = ad7768_spi_reg_write(st, AD7768_REG_POWER_CLOCK, pwr_mode); |
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if (ret < 0) |
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return ret; |
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ret = ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); |
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if (ret < 0) |
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return ret; |
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st->samp_freq = DIV_ROUND_CLOSEST(st->mclk_freq, |
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ad7768_clk_config[idx].clk_div); |
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return 0; |
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} |
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static ssize_t ad7768_sampling_freq_avail(struct device *dev, |
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struct device_attribute *attr, |
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char *buf) |
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{ |
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struct iio_dev *indio_dev = dev_to_iio_dev(dev); |
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struct ad7768_state *st = iio_priv(indio_dev); |
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unsigned int freq; |
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int i, len = 0; |
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for (i = 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { |
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freq = DIV_ROUND_CLOSEST(st->mclk_freq, |
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ad7768_clk_config[i].clk_div); |
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len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", freq); |
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} |
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buf[len - 1] = '\n'; |
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return len; |
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} |
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static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(ad7768_sampling_freq_avail); |
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static int ad7768_read_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int *val, int *val2, long info) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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int scale_uv, ret; |
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switch (info) { |
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case IIO_CHAN_INFO_RAW: |
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ret = iio_device_claim_direct_mode(indio_dev); |
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if (ret) |
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return ret; |
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ret = ad7768_scan_direct(indio_dev); |
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if (ret >= 0) |
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*val = ret; |
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iio_device_release_direct_mode(indio_dev); |
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if (ret < 0) |
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return ret; |
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return IIO_VAL_INT; |
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case IIO_CHAN_INFO_SCALE: |
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scale_uv = regulator_get_voltage(st->vref); |
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if (scale_uv < 0) |
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return scale_uv; |
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*val = (scale_uv * 2) / 1000; |
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*val2 = chan->scan_type.realbits; |
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return IIO_VAL_FRACTIONAL_LOG2; |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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*val = st->samp_freq; |
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return IIO_VAL_INT; |
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} |
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return -EINVAL; |
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} |
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static int ad7768_write_raw(struct iio_dev *indio_dev, |
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struct iio_chan_spec const *chan, |
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int val, int val2, long info) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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switch (info) { |
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case IIO_CHAN_INFO_SAMP_FREQ: |
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return ad7768_set_freq(st, val); |
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default: |
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return -EINVAL; |
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} |
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} |
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static int ad7768_read_label(struct iio_dev *indio_dev, |
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const struct iio_chan_spec *chan, char *label) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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return sprintf(label, "%s\n", st->labels[chan->channel]); |
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} |
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static struct attribute *ad7768_attributes[] = { |
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&iio_dev_attr_sampling_frequency_available.dev_attr.attr, |
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NULL |
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}; |
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static const struct attribute_group ad7768_group = { |
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.attrs = ad7768_attributes, |
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}; |
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static const struct iio_info ad7768_info = { |
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.attrs = &ad7768_group, |
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.read_raw = &ad7768_read_raw, |
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.write_raw = &ad7768_write_raw, |
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.read_label = ad7768_read_label, |
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.debugfs_reg_access = &ad7768_reg_access, |
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}; |
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static int ad7768_setup(struct ad7768_state *st) |
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{ |
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int ret; |
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/* |
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* Two writes to the SPI_RESET[1:0] bits are required to initiate |
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* a software reset. The bits must first be set to 11, and then |
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* to 10. When the sequence is detected, the reset occurs. |
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* See the datasheet, page 70. |
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*/ |
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ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x3); |
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if (ret) |
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return ret; |
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ret = ad7768_spi_reg_write(st, AD7768_REG_SYNC_RESET, 0x2); |
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if (ret) |
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return ret; |
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st->gpio_sync_in = devm_gpiod_get(&st->spi->dev, "adi,sync-in", |
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GPIOD_OUT_LOW); |
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if (IS_ERR(st->gpio_sync_in)) |
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return PTR_ERR(st->gpio_sync_in); |
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|
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/* Set the default sampling frequency to 32000 kSPS */ |
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return ad7768_set_freq(st, 32000); |
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} |
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static irqreturn_t ad7768_trigger_handler(int irq, void *p) |
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{ |
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struct iio_poll_func *pf = p; |
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struct iio_dev *indio_dev = pf->indio_dev; |
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struct ad7768_state *st = iio_priv(indio_dev); |
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int ret; |
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mutex_lock(&st->lock); |
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ret = spi_read(st->spi, &st->data.scan.chan, 3); |
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if (ret < 0) |
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goto err_unlock; |
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iio_push_to_buffers_with_timestamp(indio_dev, &st->data.scan, |
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iio_get_time_ns(indio_dev)); |
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iio_trigger_notify_done(indio_dev->trig); |
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err_unlock: |
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mutex_unlock(&st->lock); |
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return IRQ_HANDLED; |
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} |
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static irqreturn_t ad7768_interrupt(int irq, void *dev_id) |
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{ |
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struct iio_dev *indio_dev = dev_id; |
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struct ad7768_state *st = iio_priv(indio_dev); |
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|
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if (iio_buffer_enabled(indio_dev)) |
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iio_trigger_poll(st->trig); |
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else |
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complete(&st->completion); |
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return IRQ_HANDLED; |
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}; |
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static int ad7768_buffer_postenable(struct iio_dev *indio_dev) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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|
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/* |
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* Write a 1 to the LSB of the INTERFACE_FORMAT register to enter |
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* continuous read mode. Subsequent data reads do not require an |
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* initial 8-bit write to query the ADC_DATA register. |
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*/ |
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return ad7768_spi_reg_write(st, AD7768_REG_INTERFACE_FORMAT, 0x01); |
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} |
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|
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static int ad7768_buffer_predisable(struct iio_dev *indio_dev) |
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{ |
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struct ad7768_state *st = iio_priv(indio_dev); |
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|
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/* |
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* To exit continuous read mode, perform a single read of the ADC_DATA |
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* reg (0x2C), which allows further configuration of the device. |
|
*/ |
|
return ad7768_spi_reg_read(st, AD7768_REG_ADC_DATA, 3); |
|
} |
|
|
|
static const struct iio_buffer_setup_ops ad7768_buffer_ops = { |
|
.postenable = &ad7768_buffer_postenable, |
|
.predisable = &ad7768_buffer_predisable, |
|
}; |
|
|
|
static const struct iio_trigger_ops ad7768_trigger_ops = { |
|
.validate_device = iio_trigger_validate_own_device, |
|
}; |
|
|
|
static void ad7768_regulator_disable(void *data) |
|
{ |
|
struct ad7768_state *st = data; |
|
|
|
regulator_disable(st->vref); |
|
} |
|
|
|
static void ad7768_clk_disable(void *data) |
|
{ |
|
struct ad7768_state *st = data; |
|
|
|
clk_disable_unprepare(st->mclk); |
|
} |
|
|
|
static int ad7768_set_channel_label(struct iio_dev *indio_dev, |
|
int num_channels) |
|
{ |
|
struct ad7768_state *st = iio_priv(indio_dev); |
|
struct device *device = indio_dev->dev.parent; |
|
struct fwnode_handle *fwnode; |
|
struct fwnode_handle *child; |
|
const char *label; |
|
int crt_ch = 0; |
|
|
|
fwnode = dev_fwnode(device); |
|
fwnode_for_each_child_node(fwnode, child) { |
|
if (fwnode_property_read_u32(child, "reg", &crt_ch)) |
|
continue; |
|
|
|
if (crt_ch >= num_channels) |
|
continue; |
|
|
|
if (fwnode_property_read_string(child, "label", &label)) |
|
continue; |
|
|
|
st->labels[crt_ch] = label; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int ad7768_probe(struct spi_device *spi) |
|
{ |
|
struct ad7768_state *st; |
|
struct iio_dev *indio_dev; |
|
int ret; |
|
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); |
|
if (!indio_dev) |
|
return -ENOMEM; |
|
|
|
st = iio_priv(indio_dev); |
|
st->spi = spi; |
|
|
|
st->vref = devm_regulator_get(&spi->dev, "vref"); |
|
if (IS_ERR(st->vref)) |
|
return PTR_ERR(st->vref); |
|
|
|
ret = regulator_enable(st->vref); |
|
if (ret) { |
|
dev_err(&spi->dev, "Failed to enable specified vref supply\n"); |
|
return ret; |
|
} |
|
|
|
ret = devm_add_action_or_reset(&spi->dev, ad7768_regulator_disable, st); |
|
if (ret) |
|
return ret; |
|
|
|
st->mclk = devm_clk_get(&spi->dev, "mclk"); |
|
if (IS_ERR(st->mclk)) |
|
return PTR_ERR(st->mclk); |
|
|
|
ret = clk_prepare_enable(st->mclk); |
|
if (ret < 0) |
|
return ret; |
|
|
|
ret = devm_add_action_or_reset(&spi->dev, ad7768_clk_disable, st); |
|
if (ret) |
|
return ret; |
|
|
|
st->mclk_freq = clk_get_rate(st->mclk); |
|
|
|
mutex_init(&st->lock); |
|
|
|
indio_dev->channels = ad7768_channels; |
|
indio_dev->num_channels = ARRAY_SIZE(ad7768_channels); |
|
indio_dev->name = spi_get_device_id(spi)->name; |
|
indio_dev->info = &ad7768_info; |
|
indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED; |
|
|
|
ret = ad7768_setup(st); |
|
if (ret < 0) { |
|
dev_err(&spi->dev, "AD7768 setup failed\n"); |
|
return ret; |
|
} |
|
|
|
st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d", |
|
indio_dev->name, |
|
iio_device_id(indio_dev)); |
|
if (!st->trig) |
|
return -ENOMEM; |
|
|
|
st->trig->ops = &ad7768_trigger_ops; |
|
iio_trigger_set_drvdata(st->trig, indio_dev); |
|
ret = devm_iio_trigger_register(&spi->dev, st->trig); |
|
if (ret) |
|
return ret; |
|
|
|
indio_dev->trig = iio_trigger_get(st->trig); |
|
|
|
init_completion(&st->completion); |
|
|
|
ret = ad7768_set_channel_label(indio_dev, ARRAY_SIZE(ad7768_channels)); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_request_irq(&spi->dev, spi->irq, |
|
&ad7768_interrupt, |
|
IRQF_TRIGGER_RISING | IRQF_ONESHOT, |
|
indio_dev->name, indio_dev); |
|
if (ret) |
|
return ret; |
|
|
|
ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, |
|
&iio_pollfunc_store_time, |
|
&ad7768_trigger_handler, |
|
&ad7768_buffer_ops); |
|
if (ret) |
|
return ret; |
|
|
|
return devm_iio_device_register(&spi->dev, indio_dev); |
|
} |
|
|
|
static const struct spi_device_id ad7768_id_table[] = { |
|
{ "ad7768-1", 0 }, |
|
{} |
|
}; |
|
MODULE_DEVICE_TABLE(spi, ad7768_id_table); |
|
|
|
static const struct of_device_id ad7768_of_match[] = { |
|
{ .compatible = "adi,ad7768-1" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, ad7768_of_match); |
|
|
|
static struct spi_driver ad7768_driver = { |
|
.driver = { |
|
.name = "ad7768-1", |
|
.of_match_table = ad7768_of_match, |
|
}, |
|
.probe = ad7768_probe, |
|
.id_table = ad7768_id_table, |
|
}; |
|
module_spi_driver(ad7768_driver); |
|
|
|
MODULE_AUTHOR("Stefan Popa <[email protected]>"); |
|
MODULE_DESCRIPTION("Analog Devices AD7768-1 ADC driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|