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148 lines
3.5 KiB
148 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017 MediaTek Inc. |
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* Author: Chen Zhong <[email protected]> |
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* Sean Wang <[email protected]> |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_device.h> |
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#include <linux/platform_device.h> |
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#include "clk-mtk.h" |
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#include "clk-gate.h" |
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#include <dt-bindings/clock/mt7622-clk.h> |
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#define GATE_ETH(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = ð_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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} |
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static const struct mtk_gate_regs eth_cg_regs = { |
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.set_ofs = 0x30, |
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.clr_ofs = 0x30, |
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.sta_ofs = 0x30, |
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}; |
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static const struct mtk_gate eth_clks[] = { |
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GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5), |
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GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6), |
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GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7), |
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GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8), |
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GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9), |
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}; |
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static const struct mtk_gate_regs sgmii_cg_regs = { |
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.set_ofs = 0xE4, |
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.clr_ofs = 0xE4, |
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.sta_ofs = 0xE4, |
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}; |
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#define GATE_SGMII(_id, _name, _parent, _shift) { \ |
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.id = _id, \ |
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.name = _name, \ |
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.parent_name = _parent, \ |
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.regs = &sgmii_cg_regs, \ |
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.shift = _shift, \ |
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \ |
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} |
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static const struct mtk_gate sgmii_clks[] = { |
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GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en", |
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"ssusb_tx250m", 2), |
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GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en", |
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"ssusb_eq_rx250m", 3), |
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GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref", |
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"ssusb_cdr_ref", 4), |
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GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb", |
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"ssusb_cdr_fb", 5), |
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}; |
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static int clk_mt7622_ethsys_init(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); |
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mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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mtk_register_reset_controller(node, 1, 0x34); |
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return r; |
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} |
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static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) |
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{ |
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struct clk_onecell_data *clk_data; |
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struct device_node *node = pdev->dev.of_node; |
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int r; |
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clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); |
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mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), |
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clk_data); |
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r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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return r; |
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} |
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static const struct of_device_id of_match_clk_mt7622_eth[] = { |
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{ |
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.compatible = "mediatek,mt7622-ethsys", |
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.data = clk_mt7622_ethsys_init, |
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}, { |
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.compatible = "mediatek,mt7622-sgmiisys", |
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.data = clk_mt7622_sgmiisys_init, |
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}, { |
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/* sentinel */ |
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} |
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}; |
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static int clk_mt7622_eth_probe(struct platform_device *pdev) |
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{ |
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int (*clk_init)(struct platform_device *); |
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int r; |
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clk_init = of_device_get_match_data(&pdev->dev); |
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if (!clk_init) |
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return -EINVAL; |
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r = clk_init(pdev); |
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if (r) |
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dev_err(&pdev->dev, |
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"could not register clock provider: %s: %d\n", |
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pdev->name, r); |
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return r; |
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} |
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static struct platform_driver clk_mt7622_eth_drv = { |
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.probe = clk_mt7622_eth_probe, |
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.driver = { |
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.name = "clk-mt7622-eth", |
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.of_match_table = of_match_clk_mt7622_eth, |
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}, |
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}; |
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builtin_platform_driver(clk_mt7622_eth_drv);
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