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220 lines
6.5 KiB
220 lines
6.5 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Based on linux/arch/mips/kernel/cevt-r4k.c, |
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* linux/arch/mips/jmr3927/rbhma3100/setup.c |
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* |
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* Copyright 2001 MontaVista Software Inc. |
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* Copyright (C) 2000-2001 Toshiba Corporation |
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* Copyright (C) 2007 MIPS Technologies, Inc. |
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* Copyright (C) 2007 Ralf Baechle <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/sched_clock.h> |
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#include <asm/time.h> |
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#include <asm/txx9tmr.h> |
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#define TCR_BASE (TXx9_TMTCR_CCDE | TXx9_TMTCR_CRE | TXx9_TMTCR_TMODE_ITVL) |
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#define TIMER_CCD 0 /* 1/2 */ |
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#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD)) |
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struct txx9_clocksource { |
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struct clocksource cs; |
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struct txx9_tmr_reg __iomem *tmrptr; |
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}; |
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static u64 txx9_cs_read(struct clocksource *cs) |
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{ |
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struct txx9_clocksource *txx9_cs = |
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container_of(cs, struct txx9_clocksource, cs); |
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return __raw_readl(&txx9_cs->tmrptr->trr); |
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} |
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/* Use 1 bit smaller width to use full bits in that width */ |
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#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1) |
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static struct txx9_clocksource txx9_clocksource = { |
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.cs = { |
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.name = "TXx9", |
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.rating = 200, |
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.read = txx9_cs_read, |
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.mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}, |
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}; |
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static u64 notrace txx9_read_sched_clock(void) |
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{ |
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return __raw_readl(&txx9_clocksource.tmrptr->trr); |
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} |
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void __init txx9_clocksource_init(unsigned long baseaddr, |
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unsigned int imbusclk) |
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{ |
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struct txx9_tmr_reg __iomem *tmrptr; |
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clocksource_register_hz(&txx9_clocksource.cs, TIMER_CLK(imbusclk)); |
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); |
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__raw_writel(TCR_BASE, &tmrptr->tcr); |
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__raw_writel(0, &tmrptr->tisr); |
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__raw_writel(TIMER_CCD, &tmrptr->ccdr); |
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__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); |
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__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); |
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); |
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txx9_clocksource.tmrptr = tmrptr; |
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sched_clock_register(txx9_read_sched_clock, TXX9_CLOCKSOURCE_BITS, |
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TIMER_CLK(imbusclk)); |
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} |
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struct txx9_clock_event_device { |
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struct clock_event_device cd; |
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struct txx9_tmr_reg __iomem *tmrptr; |
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}; |
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static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr) |
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{ |
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/* stop and reset counter */ |
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__raw_writel(TCR_BASE, &tmrptr->tcr); |
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/* clear pending interrupt */ |
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__raw_writel(0, &tmrptr->tisr); |
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} |
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static int txx9tmr_set_state_periodic(struct clock_event_device *evt) |
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{ |
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struct txx9_clock_event_device *txx9_cd = |
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container_of(evt, struct txx9_clock_event_device, cd); |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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txx9tmr_stop_and_clear(tmrptr); |
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__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, &tmrptr->itmr); |
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/* start timer */ |
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__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> evt->shift, |
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&tmrptr->cpra); |
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); |
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return 0; |
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} |
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static int txx9tmr_set_state_oneshot(struct clock_event_device *evt) |
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{ |
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struct txx9_clock_event_device *txx9_cd = |
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container_of(evt, struct txx9_clock_event_device, cd); |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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txx9tmr_stop_and_clear(tmrptr); |
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__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr); |
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return 0; |
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} |
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static int txx9tmr_set_state_shutdown(struct clock_event_device *evt) |
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{ |
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struct txx9_clock_event_device *txx9_cd = |
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container_of(evt, struct txx9_clock_event_device, cd); |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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txx9tmr_stop_and_clear(tmrptr); |
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__raw_writel(0, &tmrptr->itmr); |
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return 0; |
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} |
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static int txx9tmr_tick_resume(struct clock_event_device *evt) |
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{ |
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struct txx9_clock_event_device *txx9_cd = |
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container_of(evt, struct txx9_clock_event_device, cd); |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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txx9tmr_stop_and_clear(tmrptr); |
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__raw_writel(TIMER_CCD, &tmrptr->ccdr); |
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__raw_writel(0, &tmrptr->itmr); |
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return 0; |
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} |
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static int txx9tmr_set_next_event(unsigned long delta, |
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struct clock_event_device *evt) |
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{ |
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struct txx9_clock_event_device *txx9_cd = |
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container_of(evt, struct txx9_clock_event_device, cd); |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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txx9tmr_stop_and_clear(tmrptr); |
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/* start timer */ |
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__raw_writel(delta, &tmrptr->cpra); |
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__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); |
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return 0; |
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} |
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static struct txx9_clock_event_device txx9_clock_event_device = { |
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.cd = { |
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.name = "TXx9", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 200, |
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.set_state_shutdown = txx9tmr_set_state_shutdown, |
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.set_state_periodic = txx9tmr_set_state_periodic, |
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.set_state_oneshot = txx9tmr_set_state_oneshot, |
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.tick_resume = txx9tmr_tick_resume, |
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.set_next_event = txx9tmr_set_next_event, |
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}, |
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}; |
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static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) |
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{ |
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struct txx9_clock_event_device *txx9_cd = dev_id; |
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struct clock_event_device *cd = &txx9_cd->cd; |
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struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr; |
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__raw_writel(0, &tmrptr->tisr); /* ack interrupt */ |
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cd->event_handler(cd); |
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return IRQ_HANDLED; |
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} |
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void __init txx9_clockevent_init(unsigned long baseaddr, int irq, |
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unsigned int imbusclk) |
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{ |
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struct clock_event_device *cd = &txx9_clock_event_device.cd; |
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struct txx9_tmr_reg __iomem *tmrptr; |
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); |
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txx9tmr_stop_and_clear(tmrptr); |
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__raw_writel(TIMER_CCD, &tmrptr->ccdr); |
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__raw_writel(0, &tmrptr->itmr); |
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txx9_clock_event_device.tmrptr = tmrptr; |
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clockevent_set_clock(cd, TIMER_CLK(imbusclk)); |
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cd->max_delta_ns = |
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clockevent_delta2ns(0xffffffff >> (32 - TXX9_TIMER_BITS), cd); |
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cd->max_delta_ticks = 0xffffffff >> (32 - TXX9_TIMER_BITS); |
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cd->min_delta_ns = clockevent_delta2ns(0xf, cd); |
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cd->min_delta_ticks = 0xf; |
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cd->irq = irq; |
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cd->cpumask = cpumask_of(0); |
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clockevents_register_device(cd); |
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if (request_irq(irq, txx9tmr_interrupt, IRQF_PERCPU | IRQF_TIMER, |
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"txx9tmr", &txx9_clock_event_device)) |
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pr_err("Failed to request irq %d (txx9tmr)\n", irq); |
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printk(KERN_INFO "TXx9: clockevent device at 0x%lx, irq %d\n", |
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baseaddr, irq); |
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} |
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void __init txx9_tmr_init(unsigned long baseaddr) |
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{ |
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struct txx9_tmr_reg __iomem *tmrptr; |
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tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); |
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/* Start once to make CounterResetEnable effective */ |
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__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); |
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/* Stop and reset the counter */ |
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__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); |
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__raw_writel(0, &tmrptr->tisr); |
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__raw_writel(0xffffffff, &tmrptr->cpra); |
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__raw_writel(0, &tmrptr->itmr); |
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__raw_writel(0, &tmrptr->ccdr); |
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__raw_writel(0, &tmrptr->pgmr); |
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iounmap(tmrptr); |
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}
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