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122 lines
3.9 KiB
122 lines
3.9 KiB
/* SPDX-License-Identifier: MIT */ |
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/* |
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* Copyright © 2021 Intel Corporation |
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*/ |
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#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */ |
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/** |
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* struct drm_i915_context_engines_parallel_submit - Configure engine for |
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* parallel submission. |
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* |
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* Setup a slot in the context engine map to allow multiple BBs to be submitted |
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* in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU |
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* in parallel. Multiple hardware contexts are created internally in the i915 |
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* run these BBs. Once a slot is configured for N BBs only N BBs can be |
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* submitted in each execbuf IOCTL and this is implicit behavior e.g. The user |
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* doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how |
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* many BBs there are based on the slot's configuration. The N BBs are the last |
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* N buffer objects or first N if I915_EXEC_BATCH_FIRST is set. |
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* |
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* The default placement behavior is to create implicit bonds between each |
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* context if each context maps to more than 1 physical engine (e.g. context is |
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* a virtual engine). Also we only allow contexts of same engine class and these |
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* contexts must be in logically contiguous order. Examples of the placement |
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* behavior described below. Lastly, the default is to not allow BBs to |
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* preempted mid BB rather insert coordinated preemption on all hardware |
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* contexts between each set of BBs. Flags may be added in the future to change |
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* both of these default behaviors. |
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* |
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* Returns -EINVAL if hardware context placement configuration is invalid or if |
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* the placement configuration isn't supported on the platform / submission |
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* interface. |
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* Returns -ENODEV if extension isn't supported on the platform / submission |
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* interface. |
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* |
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* .. code-block:: none |
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* |
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* Example 1 pseudo code: |
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* CS[X] = generic engine of same class, logical instance X |
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE |
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* set_engines(INVALID) |
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* set_parallel(engine_index=0, width=2, num_siblings=1, |
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* engines=CS[0],CS[1]) |
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* |
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* Results in the following valid placement: |
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* CS[0], CS[1] |
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* |
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* Example 2 pseudo code: |
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* CS[X] = generic engine of same class, logical instance X |
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE |
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* set_engines(INVALID) |
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* set_parallel(engine_index=0, width=2, num_siblings=2, |
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* engines=CS[0],CS[2],CS[1],CS[3]) |
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* |
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* Results in the following valid placements: |
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* CS[0], CS[1] |
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* CS[2], CS[3] |
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* |
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* This can also be thought of as 2 virtual engines described by 2-D array |
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* in the engines the field with bonds placed between each index of the |
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* virtual engines. e.g. CS[0] is bonded to CS[1], CS[2] is bonded to |
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* CS[3]. |
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* VE[0] = CS[0], CS[2] |
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* VE[1] = CS[1], CS[3] |
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* |
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* Example 3 pseudo code: |
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* CS[X] = generic engine of same class, logical instance X |
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* INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE |
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* set_engines(INVALID) |
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* set_parallel(engine_index=0, width=2, num_siblings=2, |
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* engines=CS[0],CS[1],CS[1],CS[3]) |
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* |
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* Results in the following valid and invalid placements: |
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* CS[0], CS[1] |
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* CS[1], CS[3] - Not logical contiguous, return -EINVAL |
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*/ |
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struct drm_i915_context_engines_parallel_submit { |
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/** |
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* @base: base user extension. |
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*/ |
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struct i915_user_extension base; |
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/** |
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* @engine_index: slot for parallel engine |
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*/ |
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__u16 engine_index; |
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/** |
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* @width: number of contexts per parallel engine |
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*/ |
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__u16 width; |
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/** |
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* @num_siblings: number of siblings per context |
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*/ |
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__u16 num_siblings; |
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/** |
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* @mbz16: reserved for future use; must be zero |
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*/ |
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__u16 mbz16; |
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/** |
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* @flags: all undefined flags must be zero, currently not defined flags |
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*/ |
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__u64 flags; |
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/** |
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* @mbz64: reserved for future use; must be zero |
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*/ |
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__u64 mbz64[3]; |
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/** |
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* @engines: 2-d array of engine instances to configure parallel engine |
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* |
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* length = width (i) * num_siblings (j) |
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* index = j + i * num_siblings |
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*/ |
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struct i915_engine_class_instance engines[0]; |
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} __packed; |
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