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339 lines
8.5 KiB
339 lines
8.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2014-2015 Broadcom Corporation |
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* Copyright 2014 Linaro Limited |
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*/ |
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#include <linux/cpumask.h> |
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#include <linux/delay.h> |
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#include <linux/errno.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/irqchip/irq-bcm2836.h> |
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#include <linux/jiffies.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/sched.h> |
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#include <linux/sched/clock.h> |
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#include <linux/smp.h> |
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#include <asm/cacheflush.h> |
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#include <asm/smp.h> |
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#include <asm/smp_plat.h> |
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#include <asm/smp_scu.h> |
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#include "platsmp.h" |
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/* Size of mapped Cortex A9 SCU address space */ |
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#define CORTEX_A9_SCU_SIZE 0x58 |
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#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */ |
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#define BOOT_ADDR_CPUID_MASK 0x3 |
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/* Name of device node property defining secondary boot register location */ |
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#define OF_SECONDARY_BOOT "secondary-boot-reg" |
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#define MPIDR_CPUID_BITMASK 0x3 |
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/* |
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* Enable the Cortex A9 Snoop Control Unit |
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* |
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* By the time this is called we already know there are multiple |
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* cores present. We assume we're running on a Cortex A9 processor, |
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* so any trouble getting the base address register or getting the |
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* SCU base is a problem. |
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* |
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* Return 0 if successful or an error code otherwise. |
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*/ |
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static int __init scu_a9_enable(void) |
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{ |
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unsigned long config_base; |
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void __iomem *scu_base; |
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if (!scu_a9_has_base()) { |
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pr_err("no configuration base address register!\n"); |
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return -ENXIO; |
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} |
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/* Config base address register value is zero for uniprocessor */ |
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config_base = scu_a9_get_base(); |
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if (!config_base) { |
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pr_err("hardware reports only one core\n"); |
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return -ENOENT; |
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} |
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scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE); |
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if (!scu_base) { |
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pr_err("failed to remap config base (%lu/%u) for SCU\n", |
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config_base, CORTEX_A9_SCU_SIZE); |
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return -ENOMEM; |
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} |
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scu_enable(scu_base); |
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iounmap(scu_base); /* That's the last we'll need of this */ |
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return 0; |
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} |
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static u32 secondary_boot_addr_for(unsigned int cpu) |
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{ |
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u32 secondary_boot_addr = 0; |
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struct device_node *cpu_node = of_get_cpu_node(cpu, NULL); |
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if (!cpu_node) { |
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pr_err("Failed to find device tree node for CPU%u\n", cpu); |
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return 0; |
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} |
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if (of_property_read_u32(cpu_node, |
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OF_SECONDARY_BOOT, |
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&secondary_boot_addr)) |
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pr_err("required secondary boot register not specified for CPU%u\n", |
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cpu); |
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of_node_put(cpu_node); |
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return secondary_boot_addr; |
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} |
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static int nsp_write_lut(unsigned int cpu) |
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{ |
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void __iomem *sku_rom_lut; |
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phys_addr_t secondary_startup_phy; |
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const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); |
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if (!secondary_boot_addr) |
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return -EINVAL; |
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sku_rom_lut = ioremap((phys_addr_t)secondary_boot_addr, |
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sizeof(phys_addr_t)); |
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if (!sku_rom_lut) { |
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pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); |
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return -ENOMEM; |
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} |
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secondary_startup_phy = __pa_symbol(secondary_startup); |
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BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX); |
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writel_relaxed(secondary_startup_phy, sku_rom_lut); |
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/* Ensure the write is visible to the secondary core */ |
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smp_wmb(); |
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iounmap(sku_rom_lut); |
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return 0; |
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} |
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static void __init bcm_smp_prepare_cpus(unsigned int max_cpus) |
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{ |
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const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 }; |
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/* Enable the SCU on Cortex A9 based SoCs */ |
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if (scu_a9_enable()) { |
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/* Update the CPU present map to reflect uniprocessor mode */ |
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pr_warn("failed to enable A9 SCU - disabling SMP\n"); |
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init_cpu_present(&only_cpu_0); |
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} |
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} |
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/* |
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* The ROM code has the secondary cores looping, waiting for an event. |
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* When an event occurs each core examines the bottom two bits of the |
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* secondary boot register. When a core finds those bits contain its |
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* own core id, it performs initialization, including computing its boot |
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* address by clearing the boot register value's bottom two bits. The |
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* core signals that it is beginning its execution by writing its boot |
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* address back to the secondary boot register, and finally jumps to |
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* that address. |
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* |
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* So to start a core executing we need to: |
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* - Encode the (hardware) CPU id with the bottom bits of the secondary |
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* start address. |
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* - Write that value into the secondary boot register. |
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* - Generate an event to wake up the secondary CPU(s). |
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* - Wait for the secondary boot register to be re-written, which |
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* indicates the secondary core has started. |
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*/ |
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static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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{ |
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void __iomem *boot_reg; |
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phys_addr_t boot_func; |
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u64 start_clock; |
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u32 cpu_id; |
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u32 boot_val; |
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bool timeout = false; |
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const u32 secondary_boot_addr = secondary_boot_addr_for(cpu); |
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cpu_id = cpu_logical_map(cpu); |
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if (cpu_id & ~BOOT_ADDR_CPUID_MASK) { |
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pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK); |
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return -EINVAL; |
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} |
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if (!secondary_boot_addr) |
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return -EINVAL; |
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boot_reg = ioremap((phys_addr_t)secondary_boot_addr, |
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sizeof(phys_addr_t)); |
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if (!boot_reg) { |
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pr_err("unable to map boot register for cpu %u\n", cpu_id); |
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return -ENOMEM; |
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} |
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/* |
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* Secondary cores will start in secondary_startup(), |
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* defined in "arch/arm/kernel/head.S" |
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*/ |
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boot_func = __pa_symbol(secondary_startup); |
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BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK); |
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BUG_ON(boot_func > (phys_addr_t)U32_MAX); |
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/* The core to start is encoded in the low bits */ |
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boot_val = (u32)boot_func | cpu_id; |
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writel_relaxed(boot_val, boot_reg); |
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sev(); |
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/* The low bits will be cleared once the core has started */ |
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start_clock = local_clock(); |
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while (!timeout && readl_relaxed(boot_reg) == boot_val) |
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timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS; |
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iounmap(boot_reg); |
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if (!timeout) |
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return 0; |
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pr_err("timeout waiting for cpu %u to start\n", cpu_id); |
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return -ENXIO; |
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} |
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/* Cluster Dormant Control command to bring CPU into a running state */ |
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#define CDC_CMD 6 |
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#define CDC_CMD_OFFSET 0 |
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#define CDC_CMD_REG(cpu) (CDC_CMD_OFFSET + 4*(cpu)) |
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/* |
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* BCM23550 has a Cluster Dormant Control block that keeps the core in |
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* idle state. A command needs to be sent to the block to bring the CPU |
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* into running state. |
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*/ |
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static int bcm23550_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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{ |
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void __iomem *cdc_base; |
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struct device_node *dn; |
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char *name; |
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int ret; |
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/* Make sure a CDC node exists before booting the |
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* secondary core. |
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*/ |
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name = "brcm,bcm23550-cdc"; |
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dn = of_find_compatible_node(NULL, NULL, name); |
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if (!dn) { |
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pr_err("unable to find cdc node\n"); |
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return -ENODEV; |
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} |
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cdc_base = of_iomap(dn, 0); |
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of_node_put(dn); |
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if (!cdc_base) { |
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pr_err("unable to remap cdc base register\n"); |
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return -ENOMEM; |
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} |
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/* Boot the secondary core */ |
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ret = kona_boot_secondary(cpu, idle); |
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if (ret) |
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goto out; |
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/* Bring this CPU to RUN state so that nIRQ nFIQ |
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* signals are unblocked. |
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*/ |
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writel_relaxed(CDC_CMD, cdc_base + CDC_CMD_REG(cpu)); |
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out: |
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iounmap(cdc_base); |
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return ret; |
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} |
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static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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{ |
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int ret; |
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/* |
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* After wake up, secondary core branches to the startup |
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* address programmed at SKU ROM LUT location. |
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*/ |
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ret = nsp_write_lut(cpu); |
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if (ret) { |
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pr_err("unable to write startup addr to SKU ROM LUT\n"); |
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goto out; |
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} |
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/* Send a CPU wakeup interrupt to the secondary core */ |
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arch_send_wakeup_ipi_mask(cpumask_of(cpu)); |
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out: |
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return ret; |
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} |
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static int bcm2836_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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{ |
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void __iomem *intc_base; |
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struct device_node *dn; |
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char *name; |
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name = "brcm,bcm2836-l1-intc"; |
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dn = of_find_compatible_node(NULL, NULL, name); |
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if (!dn) { |
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pr_err("unable to find intc node\n"); |
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return -ENODEV; |
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} |
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intc_base = of_iomap(dn, 0); |
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of_node_put(dn); |
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if (!intc_base) { |
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pr_err("unable to remap intc base register\n"); |
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return -ENOMEM; |
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} |
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writel(virt_to_phys(secondary_startup), |
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intc_base + LOCAL_MAILBOX3_SET0 + 16 * cpu); |
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dsb(sy); |
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sev(); |
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iounmap(intc_base); |
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return 0; |
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} |
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static const struct smp_operations kona_smp_ops __initconst = { |
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.smp_prepare_cpus = bcm_smp_prepare_cpus, |
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.smp_boot_secondary = kona_boot_secondary, |
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}; |
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method", |
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&kona_smp_ops); |
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static const struct smp_operations bcm23550_smp_ops __initconst = { |
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.smp_boot_secondary = bcm23550_boot_secondary, |
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}; |
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm23550, "brcm,bcm23550", |
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&bcm23550_smp_ops); |
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static const struct smp_operations nsp_smp_ops __initconst = { |
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.smp_prepare_cpus = bcm_smp_prepare_cpus, |
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.smp_boot_secondary = nsp_boot_secondary, |
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}; |
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CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops); |
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const struct smp_operations bcm2836_smp_ops __initconst = { |
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.smp_boot_secondary = bcm2836_boot_secondary, |
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}; |
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CPU_METHOD_OF_DECLARE(bcm_smp_bcm2836, "brcm,bcm2836-smp", &bcm2836_smp_ops);
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