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187 lines
6.2 KiB
187 lines
6.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited |
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* |
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* Derived from MIPS: |
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* Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle ([email protected]) |
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* Copyright (C) 2007 MIPS Technologies, Inc. |
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*/ |
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#include <linux/export.h> |
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#include <linux/fcntl.h> |
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#include <linux/fs.h> |
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#include <linux/highmem.h> |
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#include <linux/kernel.h> |
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#include <linux/linkage.h> |
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#include <linux/mm.h> |
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#include <linux/sched.h> |
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#include <linux/syscalls.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cpu.h> |
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#include <asm/cpu-features.h> |
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#include <asm/dma.h> |
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#include <asm/loongarch.h> |
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#include <asm/processor.h> |
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#include <asm/setup.h> |
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/* |
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* LoongArch maintains ICache/DCache coherency by hardware, |
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* we just need "ibar" to avoid instruction hazard here. |
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*/ |
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void local_flush_icache_range(unsigned long start, unsigned long end) |
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{ |
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asm volatile ("\tibar 0\n"::); |
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} |
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EXPORT_SYMBOL(local_flush_icache_range); |
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void cache_error_setup(void) |
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{ |
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extern char __weak except_vec_cex; |
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set_merr_handler(0x0, &except_vec_cex, 0x80); |
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} |
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static unsigned long icache_size __read_mostly; |
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static unsigned long dcache_size __read_mostly; |
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static unsigned long vcache_size __read_mostly; |
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static unsigned long scache_size __read_mostly; |
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static char *way_string[] = { NULL, "direct mapped", "2-way", |
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"3-way", "4-way", "5-way", "6-way", "7-way", "8-way", |
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"9-way", "10-way", "11-way", "12-way", |
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"13-way", "14-way", "15-way", "16-way", |
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}; |
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static void probe_pcache(void) |
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{ |
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struct cpuinfo_loongarch *c = ¤t_cpu_data; |
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unsigned int lsize, sets, ways; |
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unsigned int config; |
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config = read_cpucfg(LOONGARCH_CPUCFG17); |
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lsize = 1 << ((config & CPUCFG17_L1I_SIZE_M) >> CPUCFG17_L1I_SIZE); |
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sets = 1 << ((config & CPUCFG17_L1I_SETS_M) >> CPUCFG17_L1I_SETS); |
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ways = ((config & CPUCFG17_L1I_WAYS_M) >> CPUCFG17_L1I_WAYS) + 1; |
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c->icache.linesz = lsize; |
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c->icache.sets = sets; |
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c->icache.ways = ways; |
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icache_size = sets * ways * lsize; |
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c->icache.waysize = icache_size / c->icache.ways; |
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config = read_cpucfg(LOONGARCH_CPUCFG18); |
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lsize = 1 << ((config & CPUCFG18_L1D_SIZE_M) >> CPUCFG18_L1D_SIZE); |
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sets = 1 << ((config & CPUCFG18_L1D_SETS_M) >> CPUCFG18_L1D_SETS); |
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ways = ((config & CPUCFG18_L1D_WAYS_M) >> CPUCFG18_L1D_WAYS) + 1; |
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c->dcache.linesz = lsize; |
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c->dcache.sets = sets; |
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c->dcache.ways = ways; |
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dcache_size = sets * ways * lsize; |
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c->dcache.waysize = dcache_size / c->dcache.ways; |
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c->options |= LOONGARCH_CPU_PREFETCH; |
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pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", |
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icache_size >> 10, way_string[c->icache.ways], "VIPT", c->icache.linesz); |
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pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", |
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dcache_size >> 10, way_string[c->dcache.ways], "VIPT", "no aliases", c->dcache.linesz); |
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} |
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static void probe_vcache(void) |
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{ |
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struct cpuinfo_loongarch *c = ¤t_cpu_data; |
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unsigned int lsize, sets, ways; |
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unsigned int config; |
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config = read_cpucfg(LOONGARCH_CPUCFG19); |
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lsize = 1 << ((config & CPUCFG19_L2_SIZE_M) >> CPUCFG19_L2_SIZE); |
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sets = 1 << ((config & CPUCFG19_L2_SETS_M) >> CPUCFG19_L2_SETS); |
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ways = ((config & CPUCFG19_L2_WAYS_M) >> CPUCFG19_L2_WAYS) + 1; |
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c->vcache.linesz = lsize; |
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c->vcache.sets = sets; |
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c->vcache.ways = ways; |
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vcache_size = lsize * sets * ways; |
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c->vcache.waysize = vcache_size / c->vcache.ways; |
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pr_info("Unified victim cache %ldkB %s, linesize %d bytes.\n", |
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vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); |
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} |
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static void probe_scache(void) |
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{ |
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struct cpuinfo_loongarch *c = ¤t_cpu_data; |
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unsigned int lsize, sets, ways; |
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unsigned int config; |
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config = read_cpucfg(LOONGARCH_CPUCFG20); |
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lsize = 1 << ((config & CPUCFG20_L3_SIZE_M) >> CPUCFG20_L3_SIZE); |
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sets = 1 << ((config & CPUCFG20_L3_SETS_M) >> CPUCFG20_L3_SETS); |
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ways = ((config & CPUCFG20_L3_WAYS_M) >> CPUCFG20_L3_WAYS) + 1; |
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c->scache.linesz = lsize; |
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c->scache.sets = sets; |
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c->scache.ways = ways; |
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/* 4 cores. scaches are shared */ |
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scache_size = lsize * sets * ways; |
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c->scache.waysize = scache_size / c->scache.ways; |
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pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n", |
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scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); |
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} |
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void cpu_cache_init(void) |
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{ |
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probe_pcache(); |
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probe_vcache(); |
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probe_scache(); |
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shm_align_mask = PAGE_SIZE - 1; |
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} |
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static const pgprot_t protection_map[16] = { |
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[VM_NONE] = __pgprot(_CACHE_CC | _PAGE_USER | |
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_PAGE_PROTNONE | _PAGE_NO_EXEC | |
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_PAGE_NO_READ), |
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[VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC), |
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[VM_WRITE] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC), |
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[VM_WRITE | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC), |
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[VM_EXEC] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_EXEC | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_EXEC | VM_WRITE] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_EXEC | VM_WRITE | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_SHARED] = __pgprot(_CACHE_CC | _PAGE_USER | |
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_PAGE_PROTNONE | _PAGE_NO_EXEC | |
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_PAGE_NO_READ), |
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[VM_SHARED | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC), |
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[VM_SHARED | VM_WRITE] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC | _PAGE_WRITE), |
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[VM_SHARED | VM_WRITE | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_NO_EXEC | _PAGE_WRITE), |
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[VM_SHARED | VM_EXEC] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_SHARED | VM_EXEC | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT), |
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[VM_SHARED | VM_EXEC | VM_WRITE] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_WRITE), |
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[VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = __pgprot(_CACHE_CC | _PAGE_VALID | |
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_PAGE_USER | _PAGE_PRESENT | |
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_PAGE_WRITE) |
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}; |
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DECLARE_VM_GET_PAGE_PROT
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