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896 lines
24 KiB
896 lines
24 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for A2 audio system used in SGI machines |
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* Copyright (c) 2008 Thomas Bogendoerfer <[email protected]> |
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* |
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* Based on OSS code from Ladislav Michl <[email protected]>, which |
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* was based on code from Ulf Carlsson |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <linux/module.h> |
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#include <asm/sgi/hpc3.h> |
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#include <asm/sgi/ip22.h> |
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#include <sound/core.h> |
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#include <sound/control.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm-indirect.h> |
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#include <sound/initval.h> |
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#include "hal2.h" |
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static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ |
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static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ |
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module_param(index, int, 0444); |
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MODULE_PARM_DESC(index, "Index value for SGI HAL2 soundcard."); |
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module_param(id, charp, 0444); |
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MODULE_PARM_DESC(id, "ID string for SGI HAL2 soundcard."); |
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MODULE_DESCRIPTION("ALSA driver for SGI HAL2 audio"); |
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MODULE_AUTHOR("Thomas Bogendoerfer"); |
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MODULE_LICENSE("GPL"); |
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#define H2_BLOCK_SIZE 1024 |
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#define H2_BUF_SIZE 16384 |
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struct hal2_pbus { |
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struct hpc3_pbus_dmacregs *pbus; |
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int pbusnr; |
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unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */ |
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}; |
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struct hal2_desc { |
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struct hpc_dma_desc desc; |
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u32 pad; /* padding */ |
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}; |
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struct hal2_codec { |
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struct snd_pcm_indirect pcm_indirect; |
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struct snd_pcm_substream *substream; |
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unsigned char *buffer; |
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dma_addr_t buffer_dma; |
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struct hal2_desc *desc; |
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dma_addr_t desc_dma; |
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int desc_count; |
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struct hal2_pbus pbus; |
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int voices; /* mono/stereo */ |
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unsigned int sample_rate; |
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unsigned int master; /* Master frequency */ |
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unsigned short mod; /* MOD value */ |
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unsigned short inc; /* INC value */ |
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}; |
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#define H2_MIX_OUTPUT_ATT 0 |
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#define H2_MIX_INPUT_GAIN 1 |
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struct snd_hal2 { |
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struct snd_card *card; |
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struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */ |
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struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */ |
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struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */ |
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struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */ |
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struct hal2_codec dac; |
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struct hal2_codec adc; |
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}; |
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#define H2_INDIRECT_WAIT(regs) while (hal2_read(®s->isr) & H2_ISR_TSTATUS); |
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#define H2_READ_ADDR(addr) (addr | (1<<7)) |
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#define H2_WRITE_ADDR(addr) (addr) |
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static inline u32 hal2_read(u32 *reg) |
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{ |
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return __raw_readl(reg); |
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} |
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static inline void hal2_write(u32 val, u32 *reg) |
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{ |
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__raw_writel(val, reg); |
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} |
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static u32 hal2_i_read32(struct snd_hal2 *hal2, u16 addr) |
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{ |
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u32 ret; |
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struct hal2_ctl_regs *regs = hal2->ctl_regs; |
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hal2_write(H2_READ_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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ret = hal2_read(®s->idr0) & 0xffff; |
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hal2_write(H2_READ_ADDR(addr) | 0x1, ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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ret |= (hal2_read(®s->idr0) & 0xffff) << 16; |
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return ret; |
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} |
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static void hal2_i_write16(struct snd_hal2 *hal2, u16 addr, u16 val) |
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{ |
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struct hal2_ctl_regs *regs = hal2->ctl_regs; |
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hal2_write(val, ®s->idr0); |
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hal2_write(0, ®s->idr1); |
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hal2_write(0, ®s->idr2); |
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hal2_write(0, ®s->idr3); |
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hal2_write(H2_WRITE_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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} |
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static void hal2_i_write32(struct snd_hal2 *hal2, u16 addr, u32 val) |
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{ |
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struct hal2_ctl_regs *regs = hal2->ctl_regs; |
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hal2_write(val & 0xffff, ®s->idr0); |
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hal2_write(val >> 16, ®s->idr1); |
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hal2_write(0, ®s->idr2); |
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hal2_write(0, ®s->idr3); |
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hal2_write(H2_WRITE_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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} |
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static void hal2_i_setbit16(struct snd_hal2 *hal2, u16 addr, u16 bit) |
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{ |
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struct hal2_ctl_regs *regs = hal2->ctl_regs; |
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hal2_write(H2_READ_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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hal2_write((hal2_read(®s->idr0) & 0xffff) | bit, ®s->idr0); |
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hal2_write(0, ®s->idr1); |
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hal2_write(0, ®s->idr2); |
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hal2_write(0, ®s->idr3); |
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hal2_write(H2_WRITE_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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} |
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static void hal2_i_clearbit16(struct snd_hal2 *hal2, u16 addr, u16 bit) |
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{ |
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struct hal2_ctl_regs *regs = hal2->ctl_regs; |
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hal2_write(H2_READ_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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hal2_write((hal2_read(®s->idr0) & 0xffff) & ~bit, ®s->idr0); |
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hal2_write(0, ®s->idr1); |
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hal2_write(0, ®s->idr2); |
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hal2_write(0, ®s->idr3); |
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hal2_write(H2_WRITE_ADDR(addr), ®s->iar); |
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H2_INDIRECT_WAIT(regs); |
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} |
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static int hal2_gain_info(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_info *uinfo) |
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{ |
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uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; |
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uinfo->count = 2; |
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uinfo->value.integer.min = 0; |
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switch ((int)kcontrol->private_value) { |
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case H2_MIX_OUTPUT_ATT: |
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uinfo->value.integer.max = 31; |
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break; |
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case H2_MIX_INPUT_GAIN: |
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uinfo->value.integer.max = 15; |
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break; |
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} |
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return 0; |
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} |
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static int hal2_gain_get(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol); |
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u32 tmp; |
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int l, r; |
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switch ((int)kcontrol->private_value) { |
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case H2_MIX_OUTPUT_ATT: |
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tmp = hal2_i_read32(hal2, H2I_DAC_C2); |
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if (tmp & H2I_C2_MUTE) { |
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l = 0; |
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r = 0; |
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} else { |
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l = 31 - ((tmp >> H2I_C2_L_ATT_SHIFT) & 31); |
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r = 31 - ((tmp >> H2I_C2_R_ATT_SHIFT) & 31); |
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} |
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break; |
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case H2_MIX_INPUT_GAIN: |
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tmp = hal2_i_read32(hal2, H2I_ADC_C2); |
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l = (tmp >> H2I_C2_L_GAIN_SHIFT) & 15; |
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r = (tmp >> H2I_C2_R_GAIN_SHIFT) & 15; |
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break; |
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default: |
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return -EINVAL; |
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} |
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ucontrol->value.integer.value[0] = l; |
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ucontrol->value.integer.value[1] = r; |
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return 0; |
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} |
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static int hal2_gain_put(struct snd_kcontrol *kcontrol, |
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struct snd_ctl_elem_value *ucontrol) |
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{ |
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struct snd_hal2 *hal2 = snd_kcontrol_chip(kcontrol); |
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u32 old, new; |
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int l, r; |
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l = ucontrol->value.integer.value[0]; |
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r = ucontrol->value.integer.value[1]; |
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switch ((int)kcontrol->private_value) { |
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case H2_MIX_OUTPUT_ATT: |
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old = hal2_i_read32(hal2, H2I_DAC_C2); |
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new = old & ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE); |
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if (l | r) { |
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l = 31 - l; |
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r = 31 - r; |
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new |= (l << H2I_C2_L_ATT_SHIFT); |
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new |= (r << H2I_C2_R_ATT_SHIFT); |
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} else |
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new |= H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE; |
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hal2_i_write32(hal2, H2I_DAC_C2, new); |
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break; |
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case H2_MIX_INPUT_GAIN: |
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old = hal2_i_read32(hal2, H2I_ADC_C2); |
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new = old & ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M); |
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new |= (l << H2I_C2_L_GAIN_SHIFT); |
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new |= (r << H2I_C2_R_GAIN_SHIFT); |
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hal2_i_write32(hal2, H2I_ADC_C2, new); |
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break; |
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default: |
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return -EINVAL; |
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} |
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return old != new; |
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} |
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static const struct snd_kcontrol_new hal2_ctrl_headphone = { |
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
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.name = "Headphone Playback Volume", |
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.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, |
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.private_value = H2_MIX_OUTPUT_ATT, |
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.info = hal2_gain_info, |
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.get = hal2_gain_get, |
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.put = hal2_gain_put, |
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}; |
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static const struct snd_kcontrol_new hal2_ctrl_mic = { |
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, |
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.name = "Mic Capture Volume", |
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.access = SNDRV_CTL_ELEM_ACCESS_READWRITE, |
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.private_value = H2_MIX_INPUT_GAIN, |
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.info = hal2_gain_info, |
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.get = hal2_gain_get, |
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.put = hal2_gain_put, |
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}; |
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static int hal2_mixer_create(struct snd_hal2 *hal2) |
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{ |
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int err; |
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/* mute DAC */ |
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hal2_i_write32(hal2, H2I_DAC_C2, |
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H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE); |
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/* mute ADC */ |
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hal2_i_write32(hal2, H2I_ADC_C2, 0); |
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err = snd_ctl_add(hal2->card, |
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snd_ctl_new1(&hal2_ctrl_headphone, hal2)); |
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if (err < 0) |
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return err; |
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err = snd_ctl_add(hal2->card, |
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snd_ctl_new1(&hal2_ctrl_mic, hal2)); |
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if (err < 0) |
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return err; |
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return 0; |
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} |
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static irqreturn_t hal2_interrupt(int irq, void *dev_id) |
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{ |
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struct snd_hal2 *hal2 = dev_id; |
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irqreturn_t ret = IRQ_NONE; |
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/* decide what caused this interrupt */ |
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if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) { |
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snd_pcm_period_elapsed(hal2->dac.substream); |
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ret = IRQ_HANDLED; |
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} |
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if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) { |
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snd_pcm_period_elapsed(hal2->adc.substream); |
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ret = IRQ_HANDLED; |
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} |
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return ret; |
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} |
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static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate) |
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{ |
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unsigned short mod; |
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if (44100 % rate < 48000 % rate) { |
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mod = 4 * 44100 / rate; |
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codec->master = 44100; |
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} else { |
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mod = 4 * 48000 / rate; |
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codec->master = 48000; |
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} |
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codec->inc = 4; |
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codec->mod = mod; |
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rate = 4 * codec->master / mod; |
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return rate; |
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} |
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static void hal2_set_dac_rate(struct snd_hal2 *hal2) |
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{ |
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unsigned int master = hal2->dac.master; |
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int inc = hal2->dac.inc; |
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int mod = hal2->dac.mod; |
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hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0); |
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hal2_i_write32(hal2, H2I_BRES1_C2, |
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((0xffff & (inc - mod - 1)) << 16) | inc); |
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} |
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static void hal2_set_adc_rate(struct snd_hal2 *hal2) |
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{ |
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unsigned int master = hal2->adc.master; |
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int inc = hal2->adc.inc; |
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int mod = hal2->adc.mod; |
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hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0); |
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hal2_i_write32(hal2, H2I_BRES2_C2, |
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((0xffff & (inc - mod - 1)) << 16) | inc); |
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} |
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static void hal2_setup_dac(struct snd_hal2 *hal2) |
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{ |
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unsigned int fifobeg, fifoend, highwater, sample_size; |
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struct hal2_pbus *pbus = &hal2->dac.pbus; |
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/* Now we set up some PBUS information. The PBUS needs information about |
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* what portion of the fifo it will use. If it's receiving or |
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* transmitting, and finally whether the stream is little endian or big |
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* endian. The information is written later, on the start call. |
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*/ |
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sample_size = 2 * hal2->dac.voices; |
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/* Fifo should be set to hold exactly four samples. Highwater mark |
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* should be set to two samples. */ |
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highwater = (sample_size * 2) >> 1; /* halfwords */ |
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fifobeg = 0; /* playback is first */ |
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fifoend = (sample_size * 4) >> 3; /* doublewords */ |
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pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD | |
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(highwater << 8) | (fifobeg << 16) | (fifoend << 24); |
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/* We disable everything before we do anything at all */ |
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pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; |
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hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX); |
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/* Setup the HAL2 for playback */ |
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hal2_set_dac_rate(hal2); |
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/* Set endianess */ |
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hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX); |
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/* Set DMA bus */ |
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hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr)); |
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/* We are using 1st Bresenham clock generator for playback */ |
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hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT) |
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| (1 << H2I_C1_CLKID_SHIFT) |
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| (hal2->dac.voices << H2I_C1_DATAT_SHIFT)); |
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} |
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static void hal2_setup_adc(struct snd_hal2 *hal2) |
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{ |
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unsigned int fifobeg, fifoend, highwater, sample_size; |
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struct hal2_pbus *pbus = &hal2->adc.pbus; |
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sample_size = 2 * hal2->adc.voices; |
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highwater = (sample_size * 2) >> 1; /* halfwords */ |
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fifobeg = (4 * 4) >> 3; /* record is second */ |
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fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */ |
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pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD | |
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(highwater << 8) | (fifobeg << 16) | (fifoend << 24); |
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pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; |
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hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR); |
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/* Setup the HAL2 for record */ |
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hal2_set_adc_rate(hal2); |
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/* Set endianess */ |
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hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR); |
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/* Set DMA bus */ |
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hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr)); |
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/* We are using 2nd Bresenham clock generator for record */ |
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hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT) |
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| (2 << H2I_C1_CLKID_SHIFT) |
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| (hal2->adc.voices << H2I_C1_DATAT_SHIFT)); |
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} |
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static void hal2_start_dac(struct snd_hal2 *hal2) |
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{ |
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struct hal2_pbus *pbus = &hal2->dac.pbus; |
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pbus->pbus->pbdma_dptr = hal2->dac.desc_dma; |
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pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT; |
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/* enable DAC */ |
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hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX); |
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} |
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static void hal2_start_adc(struct snd_hal2 *hal2) |
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{ |
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struct hal2_pbus *pbus = &hal2->adc.pbus; |
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pbus->pbus->pbdma_dptr = hal2->adc.desc_dma; |
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pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT; |
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/* enable ADC */ |
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hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR); |
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} |
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static inline void hal2_stop_dac(struct snd_hal2 *hal2) |
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{ |
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hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; |
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/* The HAL2 itself may remain enabled safely */ |
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} |
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static inline void hal2_stop_adc(struct snd_hal2 *hal2) |
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{ |
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hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD; |
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} |
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static int hal2_alloc_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec, |
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enum dma_data_direction buffer_dir) |
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{ |
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struct device *dev = hal2->card->dev; |
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struct hal2_desc *desc; |
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dma_addr_t desc_dma, buffer_dma; |
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int count = H2_BUF_SIZE / H2_BLOCK_SIZE; |
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int i; |
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codec->buffer = dma_alloc_noncoherent(dev, H2_BUF_SIZE, &buffer_dma, |
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buffer_dir, GFP_KERNEL); |
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if (!codec->buffer) |
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return -ENOMEM; |
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desc = dma_alloc_noncoherent(dev, count * sizeof(struct hal2_desc), |
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&desc_dma, DMA_BIDIRECTIONAL, GFP_KERNEL); |
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if (!desc) { |
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dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, buffer_dma, |
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buffer_dir); |
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return -ENOMEM; |
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} |
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codec->buffer_dma = buffer_dma; |
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codec->desc_dma = desc_dma; |
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codec->desc = desc; |
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for (i = 0; i < count; i++) { |
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desc->desc.pbuf = buffer_dma + i * H2_BLOCK_SIZE; |
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desc->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE; |
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desc->desc.pnext = (i == count - 1) ? |
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desc_dma : desc_dma + (i + 1) * sizeof(struct hal2_desc); |
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desc++; |
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} |
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dma_sync_single_for_device(dev, codec->desc_dma, |
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count * sizeof(struct hal2_desc), |
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DMA_BIDIRECTIONAL); |
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codec->desc_count = count; |
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return 0; |
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} |
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|
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static void hal2_free_dmabuf(struct snd_hal2 *hal2, struct hal2_codec *codec, |
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enum dma_data_direction buffer_dir) |
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{ |
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struct device *dev = hal2->card->dev; |
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|
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dma_free_noncoherent(dev, codec->desc_count * sizeof(struct hal2_desc), |
|
codec->desc, codec->desc_dma, DMA_BIDIRECTIONAL); |
|
dma_free_noncoherent(dev, H2_BUF_SIZE, codec->buffer, codec->buffer_dma, |
|
buffer_dir); |
|
} |
|
|
|
static const struct snd_pcm_hardware hal2_pcm_hw = { |
|
.info = (SNDRV_PCM_INFO_MMAP | |
|
SNDRV_PCM_INFO_MMAP_VALID | |
|
SNDRV_PCM_INFO_INTERLEAVED | |
|
SNDRV_PCM_INFO_BLOCK_TRANSFER | |
|
SNDRV_PCM_INFO_SYNC_APPLPTR), |
|
.formats = SNDRV_PCM_FMTBIT_S16_BE, |
|
.rates = SNDRV_PCM_RATE_8000_48000, |
|
.rate_min = 8000, |
|
.rate_max = 48000, |
|
.channels_min = 2, |
|
.channels_max = 2, |
|
.buffer_bytes_max = 65536, |
|
.period_bytes_min = 1024, |
|
.period_bytes_max = 65536, |
|
.periods_min = 2, |
|
.periods_max = 1024, |
|
}; |
|
|
|
static int hal2_playback_open(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
runtime->hw = hal2_pcm_hw; |
|
return hal2_alloc_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE); |
|
} |
|
|
|
static int hal2_playback_close(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
hal2_free_dmabuf(hal2, &hal2->dac, DMA_TO_DEVICE); |
|
return 0; |
|
} |
|
|
|
static int hal2_playback_prepare(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct hal2_codec *dac = &hal2->dac; |
|
|
|
dac->voices = runtime->channels; |
|
dac->sample_rate = hal2_compute_rate(dac, runtime->rate); |
|
memset(&dac->pcm_indirect, 0, sizeof(dac->pcm_indirect)); |
|
dac->pcm_indirect.hw_buffer_size = H2_BUF_SIZE; |
|
dac->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2; |
|
dac->pcm_indirect.hw_io = dac->buffer_dma; |
|
dac->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); |
|
dac->substream = substream; |
|
hal2_setup_dac(hal2); |
|
return 0; |
|
} |
|
|
|
static int hal2_playback_trigger(struct snd_pcm_substream *substream, int cmd) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
hal2_start_dac(hal2); |
|
break; |
|
case SNDRV_PCM_TRIGGER_STOP: |
|
hal2_stop_dac(hal2); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
return 0; |
|
} |
|
|
|
static snd_pcm_uframes_t |
|
hal2_playback_pointer(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct hal2_codec *dac = &hal2->dac; |
|
|
|
return snd_pcm_indirect_playback_pointer(substream, &dac->pcm_indirect, |
|
dac->pbus.pbus->pbdma_bptr); |
|
} |
|
|
|
static void hal2_playback_transfer(struct snd_pcm_substream *substream, |
|
struct snd_pcm_indirect *rec, size_t bytes) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
unsigned char *buf = hal2->dac.buffer + rec->hw_data; |
|
|
|
memcpy(buf, substream->runtime->dma_area + rec->sw_data, bytes); |
|
dma_sync_single_for_device(hal2->card->dev, |
|
hal2->dac.buffer_dma + rec->hw_data, bytes, |
|
DMA_TO_DEVICE); |
|
|
|
} |
|
|
|
static int hal2_playback_ack(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct hal2_codec *dac = &hal2->dac; |
|
|
|
return snd_pcm_indirect_playback_transfer(substream, |
|
&dac->pcm_indirect, |
|
hal2_playback_transfer); |
|
} |
|
|
|
static int hal2_capture_open(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
runtime->hw = hal2_pcm_hw; |
|
return hal2_alloc_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE); |
|
} |
|
|
|
static int hal2_capture_close(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
hal2_free_dmabuf(hal2, &hal2->adc, DMA_FROM_DEVICE); |
|
return 0; |
|
} |
|
|
|
static int hal2_capture_prepare(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct snd_pcm_runtime *runtime = substream->runtime; |
|
struct hal2_codec *adc = &hal2->adc; |
|
|
|
adc->voices = runtime->channels; |
|
adc->sample_rate = hal2_compute_rate(adc, runtime->rate); |
|
memset(&adc->pcm_indirect, 0, sizeof(adc->pcm_indirect)); |
|
adc->pcm_indirect.hw_buffer_size = H2_BUF_SIZE; |
|
adc->pcm_indirect.hw_queue_size = H2_BUF_SIZE / 2; |
|
adc->pcm_indirect.hw_io = adc->buffer_dma; |
|
adc->pcm_indirect.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); |
|
adc->substream = substream; |
|
hal2_setup_adc(hal2); |
|
return 0; |
|
} |
|
|
|
static int hal2_capture_trigger(struct snd_pcm_substream *substream, int cmd) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
|
|
switch (cmd) { |
|
case SNDRV_PCM_TRIGGER_START: |
|
hal2_start_adc(hal2); |
|
break; |
|
case SNDRV_PCM_TRIGGER_STOP: |
|
hal2_stop_adc(hal2); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
return 0; |
|
} |
|
|
|
static snd_pcm_uframes_t |
|
hal2_capture_pointer(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct hal2_codec *adc = &hal2->adc; |
|
|
|
return snd_pcm_indirect_capture_pointer(substream, &adc->pcm_indirect, |
|
adc->pbus.pbus->pbdma_bptr); |
|
} |
|
|
|
static void hal2_capture_transfer(struct snd_pcm_substream *substream, |
|
struct snd_pcm_indirect *rec, size_t bytes) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
unsigned char *buf = hal2->adc.buffer + rec->hw_data; |
|
|
|
dma_sync_single_for_cpu(hal2->card->dev, |
|
hal2->adc.buffer_dma + rec->hw_data, bytes, |
|
DMA_FROM_DEVICE); |
|
memcpy(substream->runtime->dma_area + rec->sw_data, buf, bytes); |
|
} |
|
|
|
static int hal2_capture_ack(struct snd_pcm_substream *substream) |
|
{ |
|
struct snd_hal2 *hal2 = snd_pcm_substream_chip(substream); |
|
struct hal2_codec *adc = &hal2->adc; |
|
|
|
return snd_pcm_indirect_capture_transfer(substream, |
|
&adc->pcm_indirect, |
|
hal2_capture_transfer); |
|
} |
|
|
|
static const struct snd_pcm_ops hal2_playback_ops = { |
|
.open = hal2_playback_open, |
|
.close = hal2_playback_close, |
|
.prepare = hal2_playback_prepare, |
|
.trigger = hal2_playback_trigger, |
|
.pointer = hal2_playback_pointer, |
|
.ack = hal2_playback_ack, |
|
}; |
|
|
|
static const struct snd_pcm_ops hal2_capture_ops = { |
|
.open = hal2_capture_open, |
|
.close = hal2_capture_close, |
|
.prepare = hal2_capture_prepare, |
|
.trigger = hal2_capture_trigger, |
|
.pointer = hal2_capture_pointer, |
|
.ack = hal2_capture_ack, |
|
}; |
|
|
|
static int hal2_pcm_create(struct snd_hal2 *hal2) |
|
{ |
|
struct snd_pcm *pcm; |
|
int err; |
|
|
|
/* create first pcm device with one outputs and one input */ |
|
err = snd_pcm_new(hal2->card, "SGI HAL2 Audio", 0, 1, 1, &pcm); |
|
if (err < 0) |
|
return err; |
|
|
|
pcm->private_data = hal2; |
|
strcpy(pcm->name, "SGI HAL2"); |
|
|
|
/* set operators */ |
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, |
|
&hal2_playback_ops); |
|
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, |
|
&hal2_capture_ops); |
|
snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, |
|
NULL, 0, 1024 * 1024); |
|
|
|
return 0; |
|
} |
|
|
|
static int hal2_dev_free(struct snd_device *device) |
|
{ |
|
struct snd_hal2 *hal2 = device->device_data; |
|
|
|
free_irq(SGI_HPCDMA_IRQ, hal2); |
|
kfree(hal2); |
|
return 0; |
|
} |
|
|
|
static const struct snd_device_ops hal2_ops = { |
|
.dev_free = hal2_dev_free, |
|
}; |
|
|
|
static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3, |
|
int index) |
|
{ |
|
codec->pbus.pbusnr = index; |
|
codec->pbus.pbus = &hpc3->pbdma[index]; |
|
} |
|
|
|
static int hal2_detect(struct snd_hal2 *hal2) |
|
{ |
|
unsigned short board, major, minor; |
|
unsigned short rev; |
|
|
|
/* reset HAL2 */ |
|
hal2_write(0, &hal2->ctl_regs->isr); |
|
|
|
/* release reset */ |
|
hal2_write(H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N, |
|
&hal2->ctl_regs->isr); |
|
|
|
|
|
hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE); |
|
rev = hal2_read(&hal2->ctl_regs->rev); |
|
if (rev & H2_REV_AUDIO_PRESENT) |
|
return -ENODEV; |
|
|
|
board = (rev & H2_REV_BOARD_M) >> 12; |
|
major = (rev & H2_REV_MAJOR_CHIP_M) >> 4; |
|
minor = (rev & H2_REV_MINOR_CHIP_M); |
|
|
|
printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n", |
|
board, major, minor); |
|
|
|
return 0; |
|
} |
|
|
|
static int hal2_create(struct snd_card *card, struct snd_hal2 **rchip) |
|
{ |
|
struct snd_hal2 *hal2; |
|
struct hpc3_regs *hpc3 = hpc3c0; |
|
int err; |
|
|
|
hal2 = kzalloc(sizeof(*hal2), GFP_KERNEL); |
|
if (!hal2) |
|
return -ENOMEM; |
|
|
|
hal2->card = card; |
|
|
|
if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED, |
|
"SGI HAL2", hal2)) { |
|
printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ); |
|
kfree(hal2); |
|
return -EAGAIN; |
|
} |
|
|
|
hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0]; |
|
hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1]; |
|
hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2]; |
|
hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3]; |
|
|
|
if (hal2_detect(hal2) < 0) { |
|
kfree(hal2); |
|
return -ENODEV; |
|
} |
|
|
|
hal2_init_codec(&hal2->dac, hpc3, 0); |
|
hal2_init_codec(&hal2->adc, hpc3, 1); |
|
|
|
/* |
|
* All DMA channel interfaces in HAL2 are designed to operate with |
|
* PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles |
|
* in D5. HAL2 is a 16-bit device which can accept both big and little |
|
* endian format. It assumes that even address bytes are on high |
|
* portion of PBUS (15:8) and assumes that HPC3 is programmed to |
|
* accept a live (unsynchronized) version of P_DREQ_N from HAL2. |
|
*/ |
|
#define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \ |
|
(2 << HPC3_DMACFG_D4R_SHIFT) | \ |
|
(2 << HPC3_DMACFG_D5R_SHIFT) | \ |
|
(0 << HPC3_DMACFG_D3W_SHIFT) | \ |
|
(2 << HPC3_DMACFG_D4W_SHIFT) | \ |
|
(2 << HPC3_DMACFG_D5W_SHIFT) | \ |
|
HPC3_DMACFG_DS16 | \ |
|
HPC3_DMACFG_EVENHI | \ |
|
HPC3_DMACFG_RTIME | \ |
|
(8 << HPC3_DMACFG_BURST_SHIFT) | \ |
|
HPC3_DMACFG_DRQLIVE) |
|
/* |
|
* Ignore what's mentioned in the specification and write value which |
|
* works in The Real World (TM) |
|
*/ |
|
hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844; |
|
hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844; |
|
|
|
err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, hal2, &hal2_ops); |
|
if (err < 0) { |
|
free_irq(SGI_HPCDMA_IRQ, hal2); |
|
kfree(hal2); |
|
return err; |
|
} |
|
*rchip = hal2; |
|
return 0; |
|
} |
|
|
|
static int hal2_probe(struct platform_device *pdev) |
|
{ |
|
struct snd_card *card; |
|
struct snd_hal2 *chip; |
|
int err; |
|
|
|
err = snd_card_new(&pdev->dev, index, id, THIS_MODULE, 0, &card); |
|
if (err < 0) |
|
return err; |
|
|
|
err = hal2_create(card, &chip); |
|
if (err < 0) { |
|
snd_card_free(card); |
|
return err; |
|
} |
|
|
|
err = hal2_pcm_create(chip); |
|
if (err < 0) { |
|
snd_card_free(card); |
|
return err; |
|
} |
|
err = hal2_mixer_create(chip); |
|
if (err < 0) { |
|
snd_card_free(card); |
|
return err; |
|
} |
|
|
|
strcpy(card->driver, "SGI HAL2 Audio"); |
|
strcpy(card->shortname, "SGI HAL2 Audio"); |
|
sprintf(card->longname, "%s irq %i", |
|
card->shortname, |
|
SGI_HPCDMA_IRQ); |
|
|
|
err = snd_card_register(card); |
|
if (err < 0) { |
|
snd_card_free(card); |
|
return err; |
|
} |
|
platform_set_drvdata(pdev, card); |
|
return 0; |
|
} |
|
|
|
static int hal2_remove(struct platform_device *pdev) |
|
{ |
|
struct snd_card *card = platform_get_drvdata(pdev); |
|
|
|
snd_card_free(card); |
|
return 0; |
|
} |
|
|
|
static struct platform_driver hal2_driver = { |
|
.probe = hal2_probe, |
|
.remove = hal2_remove, |
|
.driver = { |
|
.name = "sgihal2", |
|
} |
|
}; |
|
|
|
module_platform_driver(hal2_driver);
|
|
|