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215 lines
7.0 KiB
215 lines
7.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. |
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* Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. |
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* Copyright 2010 Florian Tobias Schandinat <[email protected]> |
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*/ |
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/* |
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* basic modesetting functions |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/via-core.h> |
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#include "via_modesetting.h" |
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#include "share.h" |
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#include "debug.h" |
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void via_set_primary_timing(const struct via_display_timing *timing) |
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{ |
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struct via_display_timing raw; |
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raw.hor_total = timing->hor_total / 8 - 5; |
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raw.hor_addr = timing->hor_addr / 8 - 1; |
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raw.hor_blank_start = timing->hor_blank_start / 8 - 1; |
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raw.hor_blank_end = timing->hor_blank_end / 8 - 1; |
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raw.hor_sync_start = timing->hor_sync_start / 8; |
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raw.hor_sync_end = timing->hor_sync_end / 8; |
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raw.ver_total = timing->ver_total - 2; |
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raw.ver_addr = timing->ver_addr - 1; |
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raw.ver_blank_start = timing->ver_blank_start - 1; |
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raw.ver_blank_end = timing->ver_blank_end - 1; |
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raw.ver_sync_start = timing->ver_sync_start - 1; |
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raw.ver_sync_end = timing->ver_sync_end - 1; |
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/* unlock timing registers */ |
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via_write_reg_mask(VIACR, 0x11, 0x00, 0x80); |
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via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF); |
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via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF); |
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via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF); |
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via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F); |
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via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF); |
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via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F) |
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| (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F); |
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via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF); |
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via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01) |
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| (raw.ver_addr >> (8 - 1) & 0x02) |
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| (raw.ver_sync_start >> (8 - 2) & 0x04) |
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| (raw.ver_blank_start >> (8 - 3) & 0x08) |
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| (raw.ver_total >> (9 - 5) & 0x20) |
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| (raw.ver_addr >> (9 - 6) & 0x40) |
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| (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF); |
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via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20, |
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0x20); |
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via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF); |
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via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F); |
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via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF); |
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via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF); |
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via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF); |
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via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10) |
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| (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30); |
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via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01) |
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| (raw.ver_sync_start >> (10 - 1) & 0x02) |
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| (raw.ver_addr >> (10 - 2) & 0x04) |
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| (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F); |
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via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08); |
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/* lock timing registers */ |
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via_write_reg_mask(VIACR, 0x11, 0x80, 0x80); |
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/* reset timing control */ |
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via_write_reg_mask(VIACR, 0x17, 0x00, 0x80); |
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via_write_reg_mask(VIACR, 0x17, 0x80, 0x80); |
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} |
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void via_set_secondary_timing(const struct via_display_timing *timing) |
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{ |
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struct via_display_timing raw; |
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raw.hor_total = timing->hor_total - 1; |
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raw.hor_addr = timing->hor_addr - 1; |
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raw.hor_blank_start = timing->hor_blank_start - 1; |
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raw.hor_blank_end = timing->hor_blank_end - 1; |
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raw.hor_sync_start = timing->hor_sync_start - 1; |
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raw.hor_sync_end = timing->hor_sync_end - 1; |
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raw.ver_total = timing->ver_total - 1; |
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raw.ver_addr = timing->ver_addr - 1; |
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raw.ver_blank_start = timing->ver_blank_start - 1; |
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raw.ver_blank_end = timing->ver_blank_end - 1; |
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raw.ver_sync_start = timing->ver_sync_start - 1; |
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raw.ver_sync_end = timing->ver_sync_end - 1; |
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via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF); |
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via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF); |
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via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF); |
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via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF); |
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via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07) |
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| (raw.hor_blank_end >> (8 - 3) & 0x38) |
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| (raw.hor_sync_start >> (8 - 6) & 0xC0)); |
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via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F) |
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| (raw.hor_addr >> (8 - 4) & 0x70), 0x7F); |
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via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF); |
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via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF); |
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via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF); |
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via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF); |
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via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF); |
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via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF); |
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via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07) |
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| (raw.ver_blank_end >> (8 - 3) & 0x38) |
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| (raw.hor_sync_end >> (8 - 6) & 0x40) |
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| (raw.hor_sync_start >> (10 - 7) & 0x80)); |
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via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07) |
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| (raw.ver_addr >> (8 - 3) & 0x38) |
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| (raw.hor_blank_end >> (11 - 6) & 0x40) |
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| (raw.hor_sync_start >> (11 - 7) & 0x80)); |
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via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF); |
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via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F) |
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| (raw.ver_sync_start >> (8 - 5) & 0xE0)); |
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} |
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void via_set_primary_address(u32 addr) |
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{ |
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DEBUG_MSG(KERN_DEBUG "via_set_primary_address(0x%08X)\n", addr); |
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via_write_reg(VIACR, 0x0D, addr & 0xFF); |
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via_write_reg(VIACR, 0x0C, (addr >> 8) & 0xFF); |
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via_write_reg(VIACR, 0x34, (addr >> 16) & 0xFF); |
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via_write_reg_mask(VIACR, 0x48, (addr >> 24) & 0x1F, 0x1F); |
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} |
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void via_set_secondary_address(u32 addr) |
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{ |
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DEBUG_MSG(KERN_DEBUG "via_set_secondary_address(0x%08X)\n", addr); |
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/* secondary display supports only quadword aligned memory */ |
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via_write_reg_mask(VIACR, 0x62, (addr >> 2) & 0xFE, 0xFE); |
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via_write_reg(VIACR, 0x63, (addr >> 10) & 0xFF); |
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via_write_reg(VIACR, 0x64, (addr >> 18) & 0xFF); |
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via_write_reg_mask(VIACR, 0xA3, (addr >> 26) & 0x07, 0x07); |
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} |
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void via_set_primary_pitch(u32 pitch) |
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{ |
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DEBUG_MSG(KERN_DEBUG "via_set_primary_pitch(0x%08X)\n", pitch); |
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/* spec does not say that first adapter skips 3 bits but old |
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* code did it and seems to be reasonable in analogy to 2nd adapter |
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*/ |
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pitch = pitch >> 3; |
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via_write_reg(VIACR, 0x13, pitch & 0xFF); |
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via_write_reg_mask(VIACR, 0x35, (pitch >> (8 - 5)) & 0xE0, 0xE0); |
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} |
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void via_set_secondary_pitch(u32 pitch) |
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{ |
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DEBUG_MSG(KERN_DEBUG "via_set_secondary_pitch(0x%08X)\n", pitch); |
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pitch = pitch >> 3; |
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via_write_reg(VIACR, 0x66, pitch & 0xFF); |
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via_write_reg_mask(VIACR, 0x67, (pitch >> 8) & 0x03, 0x03); |
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via_write_reg_mask(VIACR, 0x71, (pitch >> (10 - 7)) & 0x80, 0x80); |
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} |
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void via_set_primary_color_depth(u8 depth) |
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{ |
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u8 value; |
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DEBUG_MSG(KERN_DEBUG "via_set_primary_color_depth(%d)\n", depth); |
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switch (depth) { |
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case 8: |
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value = 0x00; |
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break; |
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case 15: |
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value = 0x04; |
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break; |
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case 16: |
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value = 0x14; |
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break; |
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case 24: |
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value = 0x0C; |
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break; |
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case 30: |
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value = 0x08; |
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break; |
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default: |
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printk(KERN_WARNING "via_set_primary_color_depth: " |
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"Unsupported depth: %d\n", depth); |
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return; |
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} |
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via_write_reg_mask(VIASR, 0x15, value, 0x1C); |
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} |
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void via_set_secondary_color_depth(u8 depth) |
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{ |
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u8 value; |
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DEBUG_MSG(KERN_DEBUG "via_set_secondary_color_depth(%d)\n", depth); |
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switch (depth) { |
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case 8: |
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value = 0x00; |
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break; |
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case 16: |
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value = 0x40; |
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break; |
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case 24: |
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value = 0xC0; |
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break; |
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case 30: |
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value = 0x80; |
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break; |
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default: |
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printk(KERN_WARNING "via_set_secondary_color_depth: " |
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"Unsupported depth: %d\n", depth); |
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return; |
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} |
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via_write_reg_mask(VIACR, 0x67, value, 0xC0); |
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}
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